A reconfigurable hardware interface for a modern computing system

Philip Garcia*, Katherine Compton

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Scopus citations

Abstract

Reconfigurable hardware (RH) is used in an increasing variety of applications, many of which require support for features commonly found in general purpose systems. In this work we examine some of the challenges faced in integrating RH with general purpose processors and memory systems. We propose a new CPU-RH-memory interface that takes advantage of on-chip caches and uses virtual memory for communication. Additionally we describe the simulator model we developed to evaluate this new architecture. This work shows that an efficient interface can greatly accelerate RH applications, and provides a strong first step toward multiprocessor reconfigurable computing.

Original languageEnglish (US)
Title of host publicationProceedings 2007 IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2015
PublisherIEEE Computer Society
Pages73-81
Number of pages9
ISBN (Print)0769529402, 9780769529400
DOIs
StatePublished - 2007
Externally publishedYes
Event15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2007 - Napa, CA, United States
Duration: Apr 23 2007Apr 25 2007

Publication series

NameProceedings 2007 IEEE Symposium on Field-Programme Custom Computing Machines, FCCM 2007

Conference

Conference15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2007
Country/TerritoryUnited States
CityNapa, CA
Period4/23/074/25/07

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

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