A reconfiguration-aware floorplacer for FPGAs

The goal of this paper is to introduce a partitioning and floorplanning algorithm tailored for reconfigurable architectures deployable on FPGAs. Our proposed algorithm specifically considers the feasibility of the associated communication infrastructure for a given floorplan. Different from existing approaches, our floorplanning algorithm takes specific physical constraints such as resource distribution and the granularity of reconfiguration possible for a given FPGA device into account. These physical constraints are typically considered at the later placement stage. In order to emphasize this fundamental difference with respect to traditional floorplanners, we refer to our approach as a floorplacer.