A ReRAM-based single-NVM nonvolatile flip-flop with reduced stress-time and write-power against wide distribution in write-time by using self-write-termination scheme for nonvolatile processors in IoT era

Chieh Pu Lo; Wei Hao Chen; Zhibo Wang; Albert Lee; Kuo Hsiang Hsu; Fang Su; Ya Chin King; Chrong Jung Lin; Yongpan Liu; Huazhong Yang; Pedram Khalili; Kang Lung Wang; Meng Fan Chang

doi:10.1109/IEDM.2016.7838430

A ReRAM-based single-NVM nonvolatile flip-flop with reduced stress-time and write-power against wide distribution in write-time by using self-write-termination scheme for nonvolatile processors in IoT era

Chieh Pu Lo, Wei Hao Chen, Zhibo Wang, Albert Lee, Kuo Hsiang Hsu, Fang Su, Ya Chin King, Chrong Jung Lin, Yongpan Liu, Huazhong Yang, Pedram Khalili, Kang Lung Wang, Meng Fan Chang

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Scopus citations

Abstract

Recent nonvolatile flip-flops (nvFFs) enable the parallel movement of data locally between flip-flops (FFs) and nonvolatile memory (NVM) devices for faster system power off/on operations. The wide distribution and long period in NVM-write times of previous two-NVM-based nvFFs result in excessive store energy (Es) and over-write induced reliability degradation for NVM-write operations. This work proposes an nvFF using a single NVM (1R) with self-write-termination (SWT), capable of reducing E_S by 27+x and avoid over-write operations. In fabricated 65nm ReRAM nvProcessor testchips, the proposed SWT1R nvFFs achieved off/on operations with a 99% reduction in Es and 2.7ns SWT latency (T_SWT). For the first time, an nvFF with single NVM device is presented.

Original language	English (US)
Title of host publication	2016 IEEE International Electron Devices Meeting, IEDM 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	16.3.1-16.3.4
ISBN (Electronic)	9781509039012
DOIs	https://doi.org/10.1109/IEDM.2016.7838430
State	Published - Jan 31 2017
Event	62nd IEEE International Electron Devices Meeting, IEDM 2016 - San Francisco, United States Duration: Dec 3 2016 → Dec 7 2016

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Other

Other	62nd IEEE International Electron Devices Meeting, IEDM 2016
Country/Territory	United States
City	San Francisco
Period	12/3/16 → 12/7/16

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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10.1109/IEDM.2016.7838430

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Lo, C. P., Chen, W. H., Wang, Z., Lee, A., Hsu, K. H., Su, F., King, Y. C., Lin, C. J., Liu, Y., Yang, H., Khalili, P., Wang, K. L., & Chang, M. F. (2017). A ReRAM-based single-NVM nonvolatile flip-flop with reduced stress-time and write-power against wide distribution in write-time by using self-write-termination scheme for nonvolatile processors in IoT era. In 2016 IEEE International Electron Devices Meeting, IEDM 2016 (pp. 16.3.1-16.3.4). Article 7838430 (Technical Digest - International Electron Devices Meeting, IEDM). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2016.7838430

Lo, Chieh Pu ; Chen, Wei Hao ; Wang, Zhibo et al. / A ReRAM-based single-NVM nonvolatile flip-flop with reduced stress-time and write-power against wide distribution in write-time by using self-write-termination scheme for nonvolatile processors in IoT era. 2016 IEEE International Electron Devices Meeting, IEDM 2016. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 16.3.1-16.3.4 (Technical Digest - International Electron Devices Meeting, IEDM).

@inproceedings{c8a9b73c784649adbc3ddfa720c31a60,

title = "A ReRAM-based single-NVM nonvolatile flip-flop with reduced stress-time and write-power against wide distribution in write-time by using self-write-termination scheme for nonvolatile processors in IoT era",

abstract = "Recent nonvolatile flip-flops (nvFFs) enable the parallel movement of data locally between flip-flops (FFs) and nonvolatile memory (NVM) devices for faster system power off/on operations. The wide distribution and long period in NVM-write times of previous two-NVM-based nvFFs result in excessive store energy (Es) and over-write induced reliability degradation for NVM-write operations. This work proposes an nvFF using a single NVM (1R) with self-write-termination (SWT), capable of reducing ES by 27+x and avoid over-write operations. In fabricated 65nm ReRAM nvProcessor testchips, the proposed SWT1R nvFFs achieved off/on operations with a 99% reduction in Es and 2.7ns SWT latency (TSWT). For the first time, an nvFF with single NVM device is presented.",

author = "Lo, {Chieh Pu} and Chen, {Wei Hao} and Zhibo Wang and Albert Lee and Hsu, {Kuo Hsiang} and Fang Su and King, {Ya Chin} and Lin, {Chrong Jung} and Yongpan Liu and Huazhong Yang and Pedram Khalili and Wang, {Kang Lung} and Chang, {Meng Fan}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 62nd IEEE International Electron Devices Meeting, IEDM 2016 ; Conference date: 03-12-2016 Through 07-12-2016",

year = "2017",

month = jan,

day = "31",

doi = "10.1109/IEDM.2016.7838430",

language = "English (US)",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "16.3.1--16.3.4",

booktitle = "2016 IEEE International Electron Devices Meeting, IEDM 2016",

address = "United States",

}

Lo, CP, Chen, WH, Wang, Z, Lee, A, Hsu, KH, Su, F, King, YC, Lin, CJ, Liu, Y, Yang, H, Khalili, P, Wang, KL & Chang, MF 2017, A ReRAM-based single-NVM nonvolatile flip-flop with reduced stress-time and write-power against wide distribution in write-time by using self-write-termination scheme for nonvolatile processors in IoT era. in 2016 IEEE International Electron Devices Meeting, IEDM 2016., 7838430, Technical Digest - International Electron Devices Meeting, IEDM, Institute of Electrical and Electronics Engineers Inc., pp. 16.3.1-16.3.4, 62nd IEEE International Electron Devices Meeting, IEDM 2016, San Francisco, United States, 12/3/16. https://doi.org/10.1109/IEDM.2016.7838430

A ReRAM-based single-NVM nonvolatile flip-flop with reduced stress-time and write-power against wide distribution in write-time by using self-write-termination scheme for nonvolatile processors in IoT era. / Lo, Chieh Pu; Chen, Wei Hao; Wang, Zhibo et al.
2016 IEEE International Electron Devices Meeting, IEDM 2016. Institute of Electrical and Electronics Engineers Inc., 2017. p. 16.3.1-16.3.4 7838430 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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T1 - A ReRAM-based single-NVM nonvolatile flip-flop with reduced stress-time and write-power against wide distribution in write-time by using self-write-termination scheme for nonvolatile processors in IoT era

AU - Lo, Chieh Pu

AU - Chen, Wei Hao

AU - Wang, Zhibo

AU - Lee, Albert

AU - Hsu, Kuo Hsiang

AU - Su, Fang

AU - King, Ya Chin

AU - Lin, Chrong Jung

AU - Liu, Yongpan

AU - Yang, Huazhong

AU - Khalili, Pedram

AU - Wang, Kang Lung

AU - Chang, Meng Fan

PY - 2017/1/31

Y1 - 2017/1/31

N2 - Recent nonvolatile flip-flops (nvFFs) enable the parallel movement of data locally between flip-flops (FFs) and nonvolatile memory (NVM) devices for faster system power off/on operations. The wide distribution and long period in NVM-write times of previous two-NVM-based nvFFs result in excessive store energy (Es) and over-write induced reliability degradation for NVM-write operations. This work proposes an nvFF using a single NVM (1R) with self-write-termination (SWT), capable of reducing ES by 27+x and avoid over-write operations. In fabricated 65nm ReRAM nvProcessor testchips, the proposed SWT1R nvFFs achieved off/on operations with a 99% reduction in Es and 2.7ns SWT latency (TSWT). For the first time, an nvFF with single NVM device is presented.

AB - Recent nonvolatile flip-flops (nvFFs) enable the parallel movement of data locally between flip-flops (FFs) and nonvolatile memory (NVM) devices for faster system power off/on operations. The wide distribution and long period in NVM-write times of previous two-NVM-based nvFFs result in excessive store energy (Es) and over-write induced reliability degradation for NVM-write operations. This work proposes an nvFF using a single NVM (1R) with self-write-termination (SWT), capable of reducing ES by 27+x and avoid over-write operations. In fabricated 65nm ReRAM nvProcessor testchips, the proposed SWT1R nvFFs achieved off/on operations with a 99% reduction in Es and 2.7ns SWT latency (TSWT). For the first time, an nvFF with single NVM device is presented.

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M3 - Conference contribution

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T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 16.3.1-16.3.4

BT - 2016 IEEE International Electron Devices Meeting, IEDM 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 62nd IEEE International Electron Devices Meeting, IEDM 2016

Y2 - 3 December 2016 through 7 December 2016

ER -

Lo CP, Chen WH, Wang Z, Lee A, Hsu KH, Su F et al. A ReRAM-based single-NVM nonvolatile flip-flop with reduced stress-time and write-power against wide distribution in write-time by using self-write-termination scheme for nonvolatile processors in IoT era. In 2016 IEEE International Electron Devices Meeting, IEDM 2016. Institute of Electrical and Electronics Engineers Inc. 2017. p. 16.3.1-16.3.4. 7838430. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM.2016.7838430

A ReRAM-based single-NVM nonvolatile flip-flop with reduced stress-time and write-power against wide distribution in write-time by using self-write-termination scheme for nonvolatile processors in IoT era

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