@inproceedings{7abc3c3ac01647aa808c382c6a25450e,
title = "A RRAM-based coarse grain reconfigurable array for neural network accelerators",
abstract = "We propose a novel RRAM-based coarse grain reconfigurable array design for neural network computing. The proposed reconfigurable array design consists of RRAM-based reconfigurable AU array and the associated interconnects using novel RRAM-based multiplexer logic. A significant area saving is achieved compared with conventional design due to the simplification of logic expression as well as the saving of storage space and routing congestions from conventional switch controller. The experiments using 45nm CMOS technology show 47% area improvement and 27% performance enhancement can be achieved by using proposed RRAM-based reconfigure array technique.",
author = "Zhengyu Chen and Hai Zhou and Jie Gu",
note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 ; Conference date: 15-10-2018 Through 18-10-2018",
year = "2018",
month = jul,
day = "2",
doi = "10.1109/S3S.2018.8640182",
language = "English (US)",
series = "2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018",
address = "United States",
}