A RRAM-based coarse grain reconfigurable array for neural network accelerators

Zhengyu Chen, Hai Zhou, Jie Gu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We propose a novel RRAM-based coarse grain reconfigurable array design for neural network computing. The proposed reconfigurable array design consists of RRAM-based reconfigurable AU array and the associated interconnects using novel RRAM-based multiplexer logic. A significant area saving is achieved compared with conventional design due to the simplification of logic expression as well as the saving of storage space and routing congestions from conventional switch controller. The experiments using 45nm CMOS technology show 47% area improvement and 27% performance enhancement can be achieved by using proposed RRAM-based reconfigure array technique.

Original languageEnglish (US)
Title of host publication2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538676264
DOIs
StatePublished - Feb 11 2019
Event2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 - Burlingame, United States
Duration: Oct 15 2018Oct 18 2018

Publication series

Name2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018

Conference

Conference2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
CountryUnited States
CityBurlingame
Period10/15/1810/18/18

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Electronic, Optical and Magnetic Materials
  • Instrumentation

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