A scalable distributed shared memory architecture

Scalability of a multiprocessor architecture depends on its ability to manage interconnection network latency with increasing number of processors. Interconnection network latency can be minimized by reducing the distance traversed by a message in terms of number of nodes and wire lengths. Scalability of a DSM architecture also depends on the scalability of the coherency protocol and the associated directory storage requirements. In this paper we describe a DSM architecture based on a fat tree interconnection network with augmented switching nodes. The proposed architecture is CC-NUMA, but supports several important features of COMA architectures. The scalability of this architecture is enhanced by integrating routing and cache coherency operations, which helps in improving locality by trapping requests locally. Scalability of a DSM architecture is defined and evaluated in terms of the asymptotic speedup of an algorithm with increasing number of processors.