A simulation study of thickness effect in performance of double lateral gate junctionless transistors

Farhad Larki, Arash Dehzangi, M. N. Hamidon, Sawal Hamid Md Ali, Azman Jalar, Md Shabiul Islam

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

The electrical behaviour of double lateral gate junctionless transistors, regarding to the variation of channel thickness is investigated, through 3-D numerical simulations. The simulation results explicitly show that how the device thickness affect the on and off current and threshold voltage behavior based on variation of the carriers density and recombination rates of the carriers. As the channel thickness is decreased, the amount of bulk neutral channel getting smaller which cause a decrease in the on state current. Meanwhile, the lateral gate influence on the channel is reinforced, which cause a decrease in leakage current in the off state. Threshold voltage is decreased as the channel thickness decreases. However, the recombination rate of carriers increases with decreasing the channel thickness, due to the accumulation of minority carries and shifted to the source side of the channel.

Original languageEnglish (US)
Title of host publicationProceedings - RSM 2013
Subtitle of host publication2013 IEEE Regional Symposium on Micro and Nano Electronics
Pages89-92
Number of pages4
DOIs
StatePublished - Dec 1 2013
Event2013 IEEE Regional Symposium on Micro and Nano Electronics, RSM 2013 - Langkawi, Malaysia
Duration: Sep 25 2013Sep 27 2013

Publication series

NameProceedings - RSM 2013: 2013 IEEE Regional Symposium on Micro and Nano Electronics

Other

Other2013 IEEE Regional Symposium on Micro and Nano Electronics, RSM 2013
CountryMalaysia
CityLangkawi
Period9/25/139/27/13

Keywords

  • Junctionless transistor
  • TCAD simulation
  • lateral gate
  • thickness effect

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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