A software pipelining algorithm in high-level synthesis for FPGA architectures

Lei Gao; David Zaretsky; Gaurav Mittal; Dan Schonfeld; Prith Banerjee

doi:10.1109/ISQED.2009.4810311

A software pipelining algorithm in high-level synthesis for FPGA architectures

Lei Gao^*, David Zaretsky, Gaurav Mittal, Dan Schonfeld, Prith Banerjee

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Scopus citations

Abstract

In this paper, we present a variation of the Modulo Scheduling algorithm to exploit software pipelining in the high-level synthesis for FPGA architectures. We demonstrate the difficulties of implementing software pipelining for FPGA architectures, and propose a modified version of Modulo Scheduling that utilizes memory lifetime holes and addresses circular dependencies. Experimental results demonstrate a 35% improvement on average over the nonpipelined implementation, and 15% improvement on average over the traditional Modulo Scheduling algorithm.

Original language	English (US)
Title of host publication	Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009
Pages	297-302
Number of pages	6
DOIs	https://doi.org/10.1109/ISQED.2009.4810311
State	Published - 2009
Externally published	Yes
Event	10th International Symposium on Quality Electronic Design, ISQED 2009 - San Jose, CA, United States Duration: Mar 16 2009 → Mar 18 2009

Publication series

Name	Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009

Conference

Conference	10th International Symposium on Quality Electronic Design, ISQED 2009
Country/Territory	United States
City	San Jose, CA
Period	3/16/09 → 3/18/09

Keywords

Circular dependency
Memory address aliasing
Memory lifetime hole
Modulo Scheduling
Software pipelining

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISQED.2009.4810311

Cite this

Gao, L., Zaretsky, D., Mittal, G., Schonfeld, D., & Banerjee, P. (2009). A software pipelining algorithm in high-level synthesis for FPGA architectures. In Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009 (pp. 297-302). Article 4810311 (Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009). https://doi.org/10.1109/ISQED.2009.4810311

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title = "A software pipelining algorithm in high-level synthesis for FPGA architectures",

abstract = "In this paper, we present a variation of the Modulo Scheduling algorithm to exploit software pipelining in the high-level synthesis for FPGA architectures. We demonstrate the difficulties of implementing software pipelining for FPGA architectures, and propose a modified version of Modulo Scheduling that utilizes memory lifetime holes and addresses circular dependencies. Experimental results demonstrate a 35% improvement on average over the nonpipelined implementation, and 15% improvement on average over the traditional Modulo Scheduling algorithm.",

keywords = "Circular dependency, Memory address aliasing, Memory lifetime hole, Modulo Scheduling, Software pipelining",

author = "Lei Gao and David Zaretsky and Gaurav Mittal and Dan Schonfeld and Prith Banerjee",

year = "2009",

doi = "10.1109/ISQED.2009.4810311",

language = "English (US)",

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pages = "297--302",

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note = "10th International Symposium on Quality Electronic Design, ISQED 2009 ; Conference date: 16-03-2009 Through 18-03-2009",

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Gao, L, Zaretsky, D, Mittal, G, Schonfeld, D & Banerjee, P 2009, A software pipelining algorithm in high-level synthesis for FPGA architectures. in Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009., 4810311, Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009, pp. 297-302, 10th International Symposium on Quality Electronic Design, ISQED 2009, San Jose, CA, United States, 3/16/09. https://doi.org/10.1109/ISQED.2009.4810311

A software pipelining algorithm in high-level synthesis for FPGA architectures. / Gao, Lei; Zaretsky, David; Mittal, Gaurav et al.
Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009. 2009. p. 297-302 4810311 (Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A software pipelining algorithm in high-level synthesis for FPGA architectures

AU - Gao, Lei

AU - Zaretsky, David

AU - Mittal, Gaurav

AU - Schonfeld, Dan

AU - Banerjee, Prith

PY - 2009

Y1 - 2009

N2 - In this paper, we present a variation of the Modulo Scheduling algorithm to exploit software pipelining in the high-level synthesis for FPGA architectures. We demonstrate the difficulties of implementing software pipelining for FPGA architectures, and propose a modified version of Modulo Scheduling that utilizes memory lifetime holes and addresses circular dependencies. Experimental results demonstrate a 35% improvement on average over the nonpipelined implementation, and 15% improvement on average over the traditional Modulo Scheduling algorithm.

AB - In this paper, we present a variation of the Modulo Scheduling algorithm to exploit software pipelining in the high-level synthesis for FPGA architectures. We demonstrate the difficulties of implementing software pipelining for FPGA architectures, and propose a modified version of Modulo Scheduling that utilizes memory lifetime holes and addresses circular dependencies. Experimental results demonstrate a 35% improvement on average over the nonpipelined implementation, and 15% improvement on average over the traditional Modulo Scheduling algorithm.

KW - Circular dependency

KW - Memory address aliasing

KW - Memory lifetime hole

KW - Modulo Scheduling

KW - Software pipelining

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T3 - Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009

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Gao L, Zaretsky D, Mittal G, Schonfeld D, Banerjee P. A software pipelining algorithm in high-level synthesis for FPGA architectures. In Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009. 2009. p. 297-302. 4810311. (Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009). doi: 10.1109/ISQED.2009.4810311

A software pipelining algorithm in high-level synthesis for FPGA architectures

Abstract

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Keywords

ASJC Scopus subject areas

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