Abstract
This work presents the first 3D/4D sparse CNN (SCNN) accelerator for point cloud image recognition on low power devices. A special hopping-index rule book method and efficient data search technique were developed to mitigate the overhead of coordinate management for SCNN. A 65nm test chip for 3D/4D images was demonstrated with 7.09-13.6 TOPS/W power efficiency and state-of-the-art frame rate.
| Original language | English (US) |
|---|---|
| Title of host publication | 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 106-107 |
| Number of pages | 2 |
| ISBN (Electronic) | 9781665497725 |
| DOIs | |
| State | Published - 2022 |
| Event | 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 - Honolulu, United States Duration: Jun 12 2022 → Jun 17 2022 |
Publication series
| Name | Digest of Technical Papers - Symposium on VLSI Technology |
|---|---|
| Volume | 2022-June |
| ISSN (Print) | 0743-1562 |
Conference
| Conference | 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 |
|---|---|
| Country/Territory | United States |
| City | Honolulu |
| Period | 6/12/22 → 6/17/22 |
Funding
This work was supported in part by NSF under grant number CCF-1846424. Reference [1] S. Kim, et al. VLSISymp, 2020 [5] A. Dai, et al. CVPR, 2017 [2] D. Im, et al. VLSISymp, 2021 [6] G. Ros, et al. CVPR, 2016 [3] A. Parashar, et al. ISCA, 2017 [7] Y. Chen, et al. ISSCC, 2016 [4] C. Choy, et al. CVPR, 2019 [8] S. Song, et al. CVPR, 2015
ASJC Scopus subject areas
- Electrical and Electronic Engineering