Recently a number of heuristic based system-level synthesis algorithms have been proposed. Though these algorithms quickly generate good solutions, how close these solutions are to optimal is a question that is difficult to answer. While current exact techniques produce optimal results, they fail to produce them in reasonable time. This paper presents a synthesis algorithm that produces solutions of guaranteed quality (optimal in most cases or within a known bound) with practical synthesis times (few seconds to minutes). It takes a unified look (the lack of which is one of the main sources of sub-optimality in the heuristic techniques) at different aspects of system synthesis such as pipelining, selection, allocation, scheduling and FPGA reconfiguration. Our technique can handle both time constrained as well as resource constrained synthesis problems. We present results of our algorithm implemented as part of the Match project at Northwestern University.
|Original language||English (US)|
|Number of pages||8|
|Journal||Proceedings -Design, Automation and Test in Europe, DATE|
|State||Published - Dec 1 2000|
|Event||Design, Automation and Test in Europe Conference and Exhibition 2000, DATE 2000 - Paris, France|
Duration: Mar 27 2000 → Mar 30 2000
ASJC Scopus subject areas