A Time-Domain Computing Accelerated Image Recognition Processor with Efficient Time Encoding and Non-Linear Logic Operation

Zhengyu Chen, Jie Gu

Research output: Contribution to journalArticle

Abstract

Time-domain computing (TC) has drawn significant attention recently due to its highly efficient computation for applications such as image processing and neural network computing. This paper presents novel time-domain circuit techniques, including: 1) double-encoding strategy; 2) bit-scalable design that accelerates the performance compared with previous linear coding; and 3) shared time generator (TG) with variation-aware design technique which significantly improves the error tolerance of TC. A feature-extraction and vector-quantization processor accelerated by TC has been developed for real-time image recognition. A 55-nm prototype chip shows 72-fps/core (at 1.33 GHz) operation with up to 42% area and power saving from TC compared to the conventional digital implementation.

Original languageEnglish (US)
Article number8581434
Pages (from-to)3226-3237
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Volume54
Issue number11
DOIs
StatePublished - Nov 2019

Keywords

  • Bit-scalable design
  • double-encoding scheme
  • image processing
  • median filter (MF)
  • time-domain computing (TC)
  • winner-take-all (WTA)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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