We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic design space exploration to synthesize hardware for a field programmable gate array (FPGA) which meets the user area and frequency specifications. We present an area estimator which is used to estimate the maximum number of configurable logic blocks (CLBs) consumed by the hardware synthesized for the Xilinx XC4010 from the input MATLAB algorithm. We also present a delay estimator which finds out the delay in the logic elements in the critical path and the delay in the interconnects. The total number of CLBs predicted by us is within 16% of the actual CLB consumption and the synthesized frequency estimated by us is within an error of 13% of the actual frequency after synthesis through Synplify logic synthesis tools and after placement and routing through the XACT tools from Xilinx. Since the estimators proposed by us are fast and accurate enough, they can be used in a high level synthesis framework like ours to perform rapid design space exploration.
|Original language||English (US)|
|Number of pages||8|
|Journal||Proceedings -Design, Automation and Test in Europe, DATE|
|State||Published - Dec 1 2002|
|Event||2002 Design, Automation and Test in Europe Conference and Exhibition, DATE 2002 - Paris, France|
Duration: Mar 4 2002 → Mar 8 2002
ASJC Scopus subject areas