Adaptive Thermal Management for 3D ICs with Stacked DRAM Caches

Dawei Li; Kaicheng Zhang; Akhil Guliani; Seda Ogrenci Memik

doi:10.1145/3061639.3062197

Adaptive Thermal Management for 3D ICs with Stacked DRAM Caches

Dawei Li, Kaicheng Zhang, Akhil Guliani, Seda Ogrenci Memik

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Scopus citations

Abstract

We describe an adaptive thermal management system for 3D-ICs with stacked DRAM cache memories. We present a detailed analysis of the impact of 3D-IC hotspot aggregation on the refresh behavior of the stacked DRAM-based L3 cache. We also present the consequence of the refresh variation on the overall system performance and cache energy consumption. Our analysis demonstrates that memory intensive applications are influenced more strongly by the DRAM refresh variation. We show that there is an optimal operating point where, with a reduced clock frequency, processor cores would actually recover any performance loss induced by DRAM refresh and at the same time the cache energy consumption could be optimized. We propose a low overhead run-time method that can identify the best CPU frequency modulation factor to cool the system to minimize accelerated refresh rates in the DRAM caches. Our system can provide a customizable trade-off between performance of the processor and energy savings of the memory.

Original language	English (US)
Title of host publication	Proceedings of the 54th Annual Design Automation Conference 2017, DAC 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781450349277
DOIs	https://doi.org/10.1145/3061639.3062197
State	Published - Jun 18 2017
Event	54th Annual Design Automation Conference, DAC 2017 - Austin, United States Duration: Jun 18 2017 → Jun 22 2017

Publication series

Name	Proceedings - Design Automation Conference
Volume	Part 128280
ISSN (Print)	0738-100X

Other

Other	54th Annual Design Automation Conference, DAC 2017
Country/Territory	United States
City	Austin
Period	6/18/17 → 6/22/17

Funding

This work was partially supported by the DOE Grant DESC0012531 and NSF Grant CCF-1422489.

Keywords

3D-IC
DRAM
cache
low power design
thermal management

ASJC Scopus subject areas

Computer Science Applications
Control and Systems Engineering
Electrical and Electronic Engineering
Modeling and Simulation

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1145/3061639.3062197

Cite this

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title = "Adaptive Thermal Management for 3D ICs with Stacked DRAM Caches",

abstract = "We describe an adaptive thermal management system for 3D-ICs with stacked DRAM cache memories. We present a detailed analysis of the impact of 3D-IC hotspot aggregation on the refresh behavior of the stacked DRAM-based L3 cache. We also present the consequence of the refresh variation on the overall system performance and cache energy consumption. Our analysis demonstrates that memory intensive applications are influenced more strongly by the DRAM refresh variation. We show that there is an optimal operating point where, with a reduced clock frequency, processor cores would actually recover any performance loss induced by DRAM refresh and at the same time the cache energy consumption could be optimized. We propose a low overhead run-time method that can identify the best CPU frequency modulation factor to cool the system to minimize accelerated refresh rates in the DRAM caches. Our system can provide a customizable trade-off between performance of the processor and energy savings of the memory.",

keywords = "3D-IC, DRAM, cache, low power design, thermal management",

author = "Dawei Li and Kaicheng Zhang and Akhil Guliani and Memik, {Seda Ogrenci}",

note = "Publisher Copyright: {\textcopyright} 2017 ACM.; 54th Annual Design Automation Conference, DAC 2017 ; Conference date: 18-06-2017 Through 22-06-2017",

year = "2017",

month = jun,

day = "18",

doi = "10.1145/3061639.3062197",

language = "English (US)",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

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}

Li, D, Zhang, K, Guliani, A & Memik, SO 2017, Adaptive Thermal Management for 3D ICs with Stacked DRAM Caches. in Proceedings of the 54th Annual Design Automation Conference 2017, DAC 2017., 3, Proceedings - Design Automation Conference, vol. Part 128280, Institute of Electrical and Electronics Engineers Inc., 54th Annual Design Automation Conference, DAC 2017, Austin, United States, 6/18/17. https://doi.org/10.1145/3061639.3062197

Adaptive Thermal Management for 3D ICs with Stacked DRAM Caches. / Li, Dawei; Zhang, Kaicheng; Guliani, Akhil et al.
Proceedings of the 54th Annual Design Automation Conference 2017, DAC 2017. Institute of Electrical and Electronics Engineers Inc., 2017. 3 (Proceedings - Design Automation Conference; Vol. Part 128280).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Adaptive Thermal Management for 3D ICs with Stacked DRAM Caches

AU - Li, Dawei

AU - Zhang, Kaicheng

AU - Guliani, Akhil

AU - Memik, Seda Ogrenci

PY - 2017/6/18

Y1 - 2017/6/18

N2 - We describe an adaptive thermal management system for 3D-ICs with stacked DRAM cache memories. We present a detailed analysis of the impact of 3D-IC hotspot aggregation on the refresh behavior of the stacked DRAM-based L3 cache. We also present the consequence of the refresh variation on the overall system performance and cache energy consumption. Our analysis demonstrates that memory intensive applications are influenced more strongly by the DRAM refresh variation. We show that there is an optimal operating point where, with a reduced clock frequency, processor cores would actually recover any performance loss induced by DRAM refresh and at the same time the cache energy consumption could be optimized. We propose a low overhead run-time method that can identify the best CPU frequency modulation factor to cool the system to minimize accelerated refresh rates in the DRAM caches. Our system can provide a customizable trade-off between performance of the processor and energy savings of the memory.

AB - We describe an adaptive thermal management system for 3D-ICs with stacked DRAM cache memories. We present a detailed analysis of the impact of 3D-IC hotspot aggregation on the refresh behavior of the stacked DRAM-based L3 cache. We also present the consequence of the refresh variation on the overall system performance and cache energy consumption. Our analysis demonstrates that memory intensive applications are influenced more strongly by the DRAM refresh variation. We show that there is an optimal operating point where, with a reduced clock frequency, processor cores would actually recover any performance loss induced by DRAM refresh and at the same time the cache energy consumption could be optimized. We propose a low overhead run-time method that can identify the best CPU frequency modulation factor to cool the system to minimize accelerated refresh rates in the DRAM caches. Our system can provide a customizable trade-off between performance of the processor and energy savings of the memory.

KW - 3D-IC

KW - DRAM

KW - cache

KW - low power design

KW - thermal management

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M3 - Conference contribution

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ER -

Adaptive Thermal Management for 3D ICs with Stacked DRAM Caches

Abstract

Publication series

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Funding

Keywords

ASJC Scopus subject areas

UN SDGs

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