An adaptive clock scheme exploiting instruction-based dynamic timing slack for a gpgpu architecture

Keyphrases

• GPGPU 100%
• Timing Slack 100%
• Dynamic Timing Model 100%
• Clocking Scheme 100%
• Adaptive Clock 100%
• Graphics Processing Unit 60%
• Messenger 40%
• Energy Saving 40%
• Pipeline Stages 40%
• Elastic pipeline 40%
• Neural Network 20%
• Machine Learning 20%
• Performance Improvement 20%
• Measurement Results 20%
• Clock Period 20%
• Error Resilience 20%
• CMOS Process 20%
• Local Delay 20%
• Timing Margin 20%
• Phase-locked Loop 20%
• Static Timing Analysis 20%
• Global Phase 20%
• Loop Delay 20%
• Clock Domain 20%
• 65nm CMOS 20%
• Deterministic Dynamics 20%
• Delay-locked Loop 20%
• Clock Generator 20%
• Accuracy Degradation 20%
• Resilient Characteristics 20%
• Neural Network Inference 20%

Computer Science

• Graphics Processor 100%
• Critical Path 66%
• Pipeline Stage 66%
• Clocking Scheme 66%
• Compute Unit 66%
• Neural Network 66%
• Energy Saving 66%
• Network Inference 33%
• Clock Period 33%
• Timing Analysis 33%
• Phase Locked Loop 33%
• Open Source 33%
• Performance Improvement 33%
• Machine Learning 33%
• Learning System 33%