Abstract
Directed self-assembly (DSA) complemented with multiple patterning (MP) is an attractive next generation lithography (NGL) technique for contact-hole generation. Nevertheless, a high-quality DSA-aware layout decomposer is required to enable the technology. In this article, we introduce an efficient method which incorporates a set packing for generating DSA template candidates and a local search method. Besides, a multi-start strategy is integrated into the framework to prevent the local minima. Our framework encourages the reuse of existing coloring solvers. Hence, the development cost can significantly be reduced. In addition, for DSA multiple patterning where the number of masks is larger than two, we present an efficient iterative partition based method. Experimental results showthat comparedwith the state-of-the-artwork, our methods can achieve roughly 100× speedup for double patterning, and 78.8% conflict reduction with 5× speedup for triple patterning on the dense graphs.
| Original language | English (US) |
|---|---|
| Article number | 11 |
| Journal | ACM Transactions on Design Automation of Electronic Systems |
| Volume | 23 |
| Issue number | 1 |
| DOIs | |
| State | Published - Sep 2017 |
Funding
This research is supported partly by National Natural Science Foundation of China (NSFC) research project under grant 61376040, partly by the National Key Research and Development Program under grant 2016YFB0201304, partly by National Natural Science Foundation of China (NSFC) research project under grants 61674042, 61574046, 61574044, and 61628402, partly by the Recruitment Program of Global Experts (the Thousand Talents Plan), partly by NSF under CCF-1218906, CCF-1718570, CNS-1651695, and CNS-1441695, and partly by SRC under 2014-TS-2559. Authors’ addresses: Y. Yang and W.-S. Luk, State Key Laboratory of ASIC & System, School of Microelectronics, Fudan University, 825 Zhangheng Road, Shanghai 201203, China; emails: {14110720063, luk}@fudan.edu.cn; H. Zhou, State Key Laboratory of ASIC & System, School of Microelectronics, Fudan University, Shanghai 201203, China, and also Department of Electrical Engineering and Computer Science, Northwestern University, 2145 Sheridan Road, Evanston, IL60208-3118; email: [email protected]; D. Z. Pan, State Key Laboratory of ASIC & System, School of Microelectronics, Fudan University, Shanghai 201203, China, and also Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, Texas 78712; email: [email protected]; D. Zhou, State Key Laboratory of ASIC & System, School of Microelectronics, Fudan University, Shanghai 201203, China, and also Department of Electrical Engineering, University of Texas at Dallas, Richardson, Texas 75080, USA; email: [email protected]; C. Yan (corresponding author) and X. Zeng (corresponding author), State Key Laboratory of ASIC & System, School of Microelectronics, Fudan University, 825 Zhangheng Road, Shanghai 201203, China; emails: {yanch, xzeng}@fudan.edu.cn. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]. © 2017 ACM 1084-4309/2017/09-ART11 $15.00 https://doi.org/10.1145/3131847
Keywords
- Design for manufacturability
- Directed self-assembly
- Iterative partition
- Multiple patterning
- Multiple start points
- Set packing
ASJC Scopus subject areas
- Computer Science Applications
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering