An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation

Zhengyu Chen; Jie Gu

doi:10.1109/ASSCC.2018.8579259

An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation

Zhengyu Chen, Jie Gu

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

This paper presents novel time-domain circuit techniques including double encoding strategy, shared time generator (TG) and bit-scalable design which significantly improve the performance of time-domain signal processing (TDSP) and error tolerance. A feature-extraction and vector-quantization processor accelerated by TDSP has been developed for real-time image recognition. A 55nm prototype chip shows 72 fps/core (@1.33 GHz) operation with significant enhancement from time-domain techniques compared with conventional digital implementation.

Original language	English (US)
Title of host publication	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	257-260
Number of pages	4
ISBN (Electronic)	9781538664124
DOIs	https://doi.org/10.1109/ASSCC.2018.8579259
State	Published - Dec 14 2018
Event	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Tainan, Taiwan, Province of China Duration: Nov 5 2018 → Nov 7 2018

Publication series

Name	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings

Conference

Conference	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018
Country/Territory	Taiwan, Province of China
City	Tainan
Period	11/5/18 → 11/7/18

Keywords

bit-scalable design
double-encoding scheme
image recognition
time-domain signal processing

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASSCC.2018.8579259

Cite this

Chen, Z., & Gu, J. (2018). An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation. In 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings (pp. 257-260). [8579259] (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASSCC.2018.8579259

Chen, Zhengyu ; Gu, Jie. / An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation. 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 257-260 (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings).

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title = "An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation",

abstract = "This paper presents novel time-domain circuit techniques including double encoding strategy, shared time generator (TG) and bit-scalable design which significantly improve the performance of time-domain signal processing (TDSP) and error tolerance. A feature-extraction and vector-quantization processor accelerated by TDSP has been developed for real-time image recognition. A 55nm prototype chip shows 72 fps/core (@1.33 GHz) operation with significant enhancement from time-domain techniques compared with conventional digital implementation.",

keywords = "bit-scalable design, double-encoding scheme, image recognition, time-domain signal processing",

author = "Zhengyu Chen and Jie Gu",

year = "2018",

month = dec,

day = "14",

doi = "10.1109/ASSCC.2018.8579259",

language = "English (US)",

series = "2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "257--260",

booktitle = "2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings",

address = "United States",

note = "2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 ; Conference date: 05-11-2018 Through 07-11-2018",

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Chen, Z & Gu, J 2018, An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation. in 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings., 8579259, 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 257-260, 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018, Tainan, Taiwan, Province of China, 11/5/18. https://doi.org/10.1109/ASSCC.2018.8579259

An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation. / Chen, Zhengyu; Gu, Jie.
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. p. 257-260 8579259 (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - This paper presents novel time-domain circuit techniques including double encoding strategy, shared time generator (TG) and bit-scalable design which significantly improve the performance of time-domain signal processing (TDSP) and error tolerance. A feature-extraction and vector-quantization processor accelerated by TDSP has been developed for real-time image recognition. A 55nm prototype chip shows 72 fps/core (@1.33 GHz) operation with significant enhancement from time-domain techniques compared with conventional digital implementation.

AB - This paper presents novel time-domain circuit techniques including double encoding strategy, shared time generator (TG) and bit-scalable design which significantly improve the performance of time-domain signal processing (TDSP) and error tolerance. A feature-extraction and vector-quantization processor accelerated by TDSP has been developed for real-time image recognition. A 55nm prototype chip shows 72 fps/core (@1.33 GHz) operation with significant enhancement from time-domain techniques compared with conventional digital implementation.

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M3 - Conference contribution

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BT - 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings

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Chen Z, Gu J. An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation. In 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. p. 257-260. 8579259. (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings). doi: 10.1109/ASSCC.2018.8579259

An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Access to Document

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