An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation

Zhengyu Chen, Jie Gu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents novel time-domain circuit techniques including double encoding strategy, shared time generator (TG) and bit-scalable design which significantly improve the performance of time-domain signal processing (TDSP) and error tolerance. A feature-extraction and vector-quantization processor accelerated by TDSP has been developed for real-time image recognition. A 55nm prototype chip shows 72 fps/core (@1.33 GHz) operation with significant enhancement from time-domain techniques compared with conventional digital implementation.

Original languageEnglish (US)
Title of host publication2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages257-260
Number of pages4
ISBN (Electronic)9781538664124
DOIs
StatePublished - Dec 14 2018
Event2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Tainan, Taiwan, Province of China
Duration: Nov 5 2018Nov 7 2018

Publication series

Name2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings

Conference

Conference2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018
CountryTaiwan, Province of China
CityTainan
Period11/5/1811/7/18

Fingerprint

Image recognition
Particle accelerators
Signal processing
Vector quantization
Feature extraction
Networks (circuits)

Keywords

  • bit-scalable design
  • double-encoding scheme
  • image recognition
  • time-domain signal processing

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Chen, Z., & Gu, J. (2018). An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation. In 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings (pp. 257-260). [8579259] (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASSCC.2018.8579259
Chen, Zhengyu ; Gu, Jie. / An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation. 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 257-260 (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings).
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Chen, Z & Gu, J 2018, An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation. in 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings., 8579259, 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 257-260, 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018, Tainan, Taiwan, Province of China, 11/5/18. https://doi.org/10.1109/ASSCC.2018.8579259

An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation. / Chen, Zhengyu; Gu, Jie.

2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. p. 257-260 8579259 (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Chen Z, Gu J. An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation. In 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. p. 257-260. 8579259. (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings). https://doi.org/10.1109/ASSCC.2018.8579259