An Instruction-Driven Adaptive Clock Management Through Dynamic Phase Scaling and Compiler Assistance for a Low Power Microprocessor

Keyphrases

• Compiler Assisted 100%
• Clock Management 100%
• Dynamic Phase 100%
• Low-power Microprocessor 100%
• Adaptive Clock 100%
• Performance Improvement 66%
• Design Methodology 33%
• Temperature Variation 33%
• Time Variation 33%
• Process Variation 33%
• Compiler 33%
• Cross-layer Design 33%
• Clock Period 33%
• Compiler Optimization 33%
• Voltage Variation 33%
• Optimization Scheme 33%
• Processing Temperature 33%
• Instruction Level 33%
• Management Scheme 33%
• Timing Slack 33%
• CMOS Process 33%
• Dynamic Voltage Frequency Scaling 33%
• Dynamic Voltage Scaling 33%
• Calibration Scheme 33%
• Instruction Sets 33%
• All-digital Phase-locked Loop (ADPLL) 33%
• Instruction Sequences 33%
• Dynamic Timing Model 33%
• ARMv7 33%
• Scale Operation 33%
• Energy-saving Benefits 33%
• Pipelined Architecture 33%
• Timing Calibration 33%

Computer Science

• Performance Improvement 100%
• Clock Period 50%
• Dynamic Voltage and Frequency Scaling 50%
• Compiler Optimization 50%
• Phase Locked Loop 50%
• Instruction Sequence 50%
• Pipeline Architecture 50%
• Energy Saving 50%