Keyphrases
Adaptive Clock
100%
All-digital Phase-locked Loop (ADPLL)
33%
ARMv7
33%
Calibration Scheme
33%
Clock Management
100%
Clock Period
33%
CMOS Process
33%
Compiler
33%
Compiler Assisted
100%
Compiler Optimization
33%
Cross-layer Design
33%
Design Methodology
33%
Dynamic Phase
100%
Dynamic Timing Model
33%
Dynamic Voltage Frequency Scaling
33%
Dynamic Voltage Scaling
33%
Energy-saving Benefits
33%
Instruction Level
33%
Instruction Sequences
33%
Instruction Sets
33%
Low-power Microprocessor
100%
Management Scheme
33%
Optimization Scheme
33%
Performance Improvement
66%
Pipelined Architecture
33%
Process Variation
33%
Processing Temperature
33%
Scale Operation
33%
Temperature Variation
33%
Time Variation
33%
Timing Calibration
33%
Timing Slack
33%
Voltage Variation
33%
Computer Science
Clock Period
50%
Compiler Optimization
50%
Dynamic Voltage and Frequency Scaling
50%
Energy Saving
50%
Instruction Sequence
50%
Performance Improvement
100%
Phase Locked Loop
50%
Pipeline Architecture
50%