An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor

Tianyu Jia; Russell E Joseph; Jie Gu

doi:10.1109/ESSCIRC.2018.8494244

An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor

Tianyu Jia, Russell E Joseph, Jie Gu

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

This paper presents an adaptive clock phase scaling operation based on the dynamic instruction timing variation for a low power microprocessor. Through the use of instruction timing encoding and multi-phase all-digital PLL, a dynamic clock phase modulation is realized at the granularity of instruction level. In addition, an online instruction calibration scheme is proposed to characterize the instruction timing under PVT variations, which is also integrated with conventional DVFS. The implementation on a 55nm ARM core design shows a 15% performance improvement from proposed clock scheme, and additional 5% improvement from online calibration. The performance improvement can be equivalently converted to up to 28% energy saving benefit.

Original language	English (US)
Title of host publication	ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	158-161
Number of pages	4
ISBN (Electronic)	9781538654040
DOIs	https://doi.org/10.1109/ESSCIRC.2018.8494244
State	Published - Oct 16 2018
Event	44th IEEE European Solid State Circuits Conference, ESSCIRC 2018 - Dresden, Germany Duration: Sep 3 2018 → Sep 6 2018

Publication series

Name	ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference

Conference

Conference	44th IEEE European Solid State Circuits Conference, ESSCIRC 2018
Country/Territory	Germany
City	Dresden
Period	9/3/18 → 9/6/18

Funding

ACKNOWLEDGMENT This work is supported in part by NSF grants CCF-1116610 and CCF-1618065.

Keywords

Adaptive clock
all-digital PLL
instruction timing
online calibration
phase scaling operation

ASJC Scopus subject areas

Electrical and Electronic Engineering
Instrumentation

Access to Document

10.1109/ESSCIRC.2018.8494244

Cite this

Jia, T., Joseph, R. E., & Gu, J. (2018). An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor. In ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (pp. 158-161). Article 8494244 (ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ESSCIRC.2018.8494244

Jia, Tianyu ; Joseph, Russell E ; Gu, Jie. / An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor. ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 158-161 (ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference).

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title = "An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor",

abstract = "This paper presents an adaptive clock phase scaling operation based on the dynamic instruction timing variation for a low power microprocessor. Through the use of instruction timing encoding and multi-phase all-digital PLL, a dynamic clock phase modulation is realized at the granularity of instruction level. In addition, an online instruction calibration scheme is proposed to characterize the instruction timing under PVT variations, which is also integrated with conventional DVFS. The implementation on a 55nm ARM core design shows a 15% performance improvement from proposed clock scheme, and additional 5% improvement from online calibration. The performance improvement can be equivalently converted to up to 28% energy saving benefit.",

keywords = "Adaptive clock, all-digital PLL, instruction timing, online calibration, phase scaling operation",

author = "Tianyu Jia and Joseph, {Russell E} and Jie Gu",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 44th IEEE European Solid State Circuits Conference, ESSCIRC 2018 ; Conference date: 03-09-2018 Through 06-09-2018",

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Jia, T, Joseph, RE & Gu, J 2018, An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor. in ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference., 8494244, ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., pp. 158-161, 44th IEEE European Solid State Circuits Conference, ESSCIRC 2018, Dresden, Germany, 9/3/18. https://doi.org/10.1109/ESSCIRC.2018.8494244

An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor. / Jia, Tianyu; Joseph, Russell E ; Gu, Jie.
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 2018. p. 158-161 8494244 (ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - This paper presents an adaptive clock phase scaling operation based on the dynamic instruction timing variation for a low power microprocessor. Through the use of instruction timing encoding and multi-phase all-digital PLL, a dynamic clock phase modulation is realized at the granularity of instruction level. In addition, an online instruction calibration scheme is proposed to characterize the instruction timing under PVT variations, which is also integrated with conventional DVFS. The implementation on a 55nm ARM core design shows a 15% performance improvement from proposed clock scheme, and additional 5% improvement from online calibration. The performance improvement can be equivalently converted to up to 28% energy saving benefit.

AB - This paper presents an adaptive clock phase scaling operation based on the dynamic instruction timing variation for a low power microprocessor. Through the use of instruction timing encoding and multi-phase all-digital PLL, a dynamic clock phase modulation is realized at the granularity of instruction level. In addition, an online instruction calibration scheme is proposed to characterize the instruction timing under PVT variations, which is also integrated with conventional DVFS. The implementation on a 55nm ARM core design shows a 15% performance improvement from proposed clock scheme, and additional 5% improvement from online calibration. The performance improvement can be equivalently converted to up to 28% energy saving benefit.

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Jia T, Joseph RE , Gu J. An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor. In ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc. 2018. p. 158-161. 8494244. (ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference). doi: 10.1109/ESSCIRC.2018.8494244

An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor

Abstract

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Funding

Keywords

ASJC Scopus subject areas

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