An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper presents an adaptive clock phase scaling operation based on the dynamic instruction timing variation for a low power microprocessor. Through the use of instruction timing encoding and multi-phase all-digital PLL, a dynamic clock phase modulation is realized at the granularity of instruction level. In addition, an online instruction calibration scheme is proposed to characterize the instruction timing under PVT variations, which is also integrated with conventional DVFS. The implementation on a 55nm ARM core design shows a 15% performance improvement from proposed clock scheme, and additional 5% improvement from online calibration. The performance improvement can be equivalently converted to up to 28% energy saving benefit.

Original languageEnglish (US)
Title of host publicationESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages158-161
Number of pages4
ISBN (Electronic)9781538654040
DOIs
StatePublished - Oct 16 2018
Event44th IEEE European Solid State Circuits Conference, ESSCIRC 2018 - Dresden, Germany
Duration: Sep 3 2018Sep 6 2018

Publication series

NameESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference

Conference

Conference44th IEEE European Solid State Circuits Conference, ESSCIRC 2018
CountryGermany
CityDresden
Period9/3/189/6/18

Fingerprint

microprocessors
clocks
Microprocessor chips
Clocks
coding
education
time measurement
Calibration
scaling
Phase modulation
Phase locked loops
Energy conservation
phase modulation
energy

Keywords

  • Adaptive clock
  • all-digital PLL
  • instruction timing
  • online calibration
  • phase scaling operation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Instrumentation

Cite this

Jia, T., Joseph, R. E., & Gu, J. (2018). An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor. In ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (pp. 158-161). [8494244] (ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ESSCIRC.2018.8494244
Jia, Tianyu ; Joseph, Russell E ; Gu, Jie. / An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor. ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 158-161 (ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference).
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abstract = "This paper presents an adaptive clock phase scaling operation based on the dynamic instruction timing variation for a low power microprocessor. Through the use of instruction timing encoding and multi-phase all-digital PLL, a dynamic clock phase modulation is realized at the granularity of instruction level. In addition, an online instruction calibration scheme is proposed to characterize the instruction timing under PVT variations, which is also integrated with conventional DVFS. The implementation on a 55nm ARM core design shows a 15{\%} performance improvement from proposed clock scheme, and additional 5{\%} improvement from online calibration. The performance improvement can be equivalently converted to up to 28{\%} energy saving benefit.",
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Jia, T, Joseph, RE & Gu, J 2018, An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor. in ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference., 8494244, ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., pp. 158-161, 44th IEEE European Solid State Circuits Conference, ESSCIRC 2018, Dresden, Germany, 9/3/18. https://doi.org/10.1109/ESSCIRC.2018.8494244

An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor. / Jia, Tianyu; Joseph, Russell E; Gu, Jie.

ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 2018. p. 158-161 8494244 (ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Jia T, Joseph RE, Gu J. An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor. In ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc. 2018. p. 158-161. 8494244. (ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference). https://doi.org/10.1109/ESSCIRC.2018.8494244