@inproceedings{a4aaf559e3b6477db2441c78ea31c51f,
title = "An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor",
abstract = "This paper presents an adaptive clock phase scaling operation based on the dynamic instruction timing variation for a low power microprocessor. Through the use of instruction timing encoding and multi-phase all-digital PLL, a dynamic clock phase modulation is realized at the granularity of instruction level. In addition, an online instruction calibration scheme is proposed to characterize the instruction timing under PVT variations, which is also integrated with conventional DVFS. The implementation on a 55nm ARM core design shows a 15% performance improvement from proposed clock scheme, and additional 5% improvement from online calibration. The performance improvement can be equivalently converted to up to 28% energy saving benefit.",
keywords = "Adaptive clock, all-digital PLL, instruction timing, online calibration, phase scaling operation",
author = "Tianyu Jia and Joseph, {Russell E} and Jie Gu",
note = "Funding Information: ACKNOWLEDGMENT This work is supported in part by NSF grants CCF-1116610 and CCF-1618065.; 44th IEEE European Solid State Circuits Conference, ESSCIRC 2018 ; Conference date: 03-09-2018 Through 06-09-2018",
year = "2018",
month = oct,
day = "16",
doi = "10.1109/ESSCIRC.2018.8494244",
language = "English (US)",
series = "ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "158--161",
booktitle = "ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference",
address = "United States",
}