Abstract
This paper presents an adaptive clock phase scaling operation based on the dynamic instruction timing variation for a low power microprocessor. Through the use of instruction timing encoding and multi-phase all-digital PLL, a dynamic clock phase modulation is realized at the granularity of instruction level. In addition, an online instruction calibration scheme is proposed to characterize the instruction timing under PVT variations, which is also integrated with conventional DVFS. The implementation on a 55nm ARM core design shows a 15% performance improvement from proposed clock scheme, and additional 5% improvement from online calibration. The performance improvement can be equivalently converted to up to 28% energy saving benefit.
| Original language | English (US) |
|---|---|
| Title of host publication | ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 158-161 |
| Number of pages | 4 |
| ISBN (Electronic) | 9781538654040 |
| DOIs | |
| State | Published - Oct 16 2018 |
| Event | 44th IEEE European Solid State Circuits Conference, ESSCIRC 2018 - Dresden, Germany Duration: Sep 3 2018 → Sep 6 2018 |
Publication series
| Name | ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference |
|---|
Conference
| Conference | 44th IEEE European Solid State Circuits Conference, ESSCIRC 2018 |
|---|---|
| Country | Germany |
| City | Dresden |
| Period | 9/3/18 → 9/6/18 |
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Keywords
- Adaptive clock
- all-digital PLL
- instruction timing
- online calibration
- phase scaling operation
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Instrumentation
Cite this
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An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor. / Jia, Tianyu; Joseph, Russell E; Gu, Jie.
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., 2018. p. 158-161 8494244 (ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor
AU - Jia, Tianyu
AU - Joseph, Russell E
AU - Gu, Jie
PY - 2018/10/16
Y1 - 2018/10/16
N2 - This paper presents an adaptive clock phase scaling operation based on the dynamic instruction timing variation for a low power microprocessor. Through the use of instruction timing encoding and multi-phase all-digital PLL, a dynamic clock phase modulation is realized at the granularity of instruction level. In addition, an online instruction calibration scheme is proposed to characterize the instruction timing under PVT variations, which is also integrated with conventional DVFS. The implementation on a 55nm ARM core design shows a 15% performance improvement from proposed clock scheme, and additional 5% improvement from online calibration. The performance improvement can be equivalently converted to up to 28% energy saving benefit.
AB - This paper presents an adaptive clock phase scaling operation based on the dynamic instruction timing variation for a low power microprocessor. Through the use of instruction timing encoding and multi-phase all-digital PLL, a dynamic clock phase modulation is realized at the granularity of instruction level. In addition, an online instruction calibration scheme is proposed to characterize the instruction timing under PVT variations, which is also integrated with conventional DVFS. The implementation on a 55nm ARM core design shows a 15% performance improvement from proposed clock scheme, and additional 5% improvement from online calibration. The performance improvement can be equivalently converted to up to 28% energy saving benefit.
KW - Adaptive clock
KW - all-digital PLL
KW - instruction timing
KW - online calibration
KW - phase scaling operation
UR - http://www.scopus.com/inward/record.url?scp=85056797475&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85056797475&partnerID=8YFLogxK
U2 - 10.1109/ESSCIRC.2018.8494244
DO - 10.1109/ESSCIRC.2018.8494244
M3 - Conference contribution
AN - SCOPUS:85056797475
T3 - ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference
SP - 158
EP - 161
BT - ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference
PB - Institute of Electrical and Electronics Engineers Inc.
ER -