Array-Level Analysis of Magneto-Electric Random-Access Memory for High-Performance Embedded Applications

Hochul Lee*, Albert Lee, Farbod Ebrahimi, Pedram Khalili Amiri, Kang L. Wang

*Corresponding author for this work

Research output: Contribution to journalArticle

2 Scopus citations

Abstract

An array-level evaluation of magneto-electric random-access memory (MeRAM) is conducted by comparing its performance with that of other embedded technologies. We consider MeRAM cells with one transistor and one magnetic tunnel junction (1T-1MTJ) structure, where writing of the two-terminal MTJ bit is performed by precessional reorientation of the magnetization via voltage control of the magnetic anisotropy. We consider an accurate resistance-capacitance load on the critical path by including capacitive and resistive effects on the bit lines, word lines, and source lines, because the access time and energy consumption are strongly affected by the parasitics. We then estimate the write access time, read access time, write energy, and area of each memory technology based on 28 nm complementary metal-oxide-semiconductor model parameters under two different conditions: (i) fixed array capacity (512 × 512 bits = 256 Kbits) and (ii) fixed array area (200μm × 200μm). We discuss the tradeoffs and advantages of MeRAM compared to embedded SRAM, embedded DRAM (eDRAM), stand-alone DRAM, and embedded spin-transfer torque magnetic random-access memory.

Original languageEnglish (US)
Article number4305905
JournalIEEE Magnetics Letters
Volume8
DOIs
StatePublished - Jan 1 2017

Keywords

  • DRAM
  • SRAM
  • Spintronic memory and logic
  • embedded DRAM (eDRAM)
  • magneto-electric random-access memory (MeRAM)
  • spin electronics
  • spin transfer torque magnetic random-access memory (STT-MRAM)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials

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