Automated design of self-adjusting pipelines

Jieyi Long*, Seda Ogrenci Memik

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations


We propose a self-adjusting pipeline structure to enhance chip performance and robustness considering the effects of process variations. We achieve this by introducing delay sensors to monitor internal timing violations within a pipeline stage and variable clock skew buffers to adjust the timing of the pipeline stage based on the feedback from the delay sensors. Furthermore, we formulate the delay sensor insertion and variable clock skew configuration problem as a stochastic mixed-integer programming problem and propose a simulated-annealing based algorithm to solve it. A comparison between the designs with and without the self-adjusting enhancement reveals that, we are able to improve the average performance of a batch of chips by 9.5%.

Original languageEnglish (US)
Title of host publicationProceedings of the 45th Design Automation Conference, DAC
Number of pages6
StatePublished - Sep 17 2008
Event45th Design Automation Conference, DAC - Anaheim, CA, United States
Duration: Jun 8 2008Jun 13 2008


Other45th Design Automation Conference, DAC
Country/TerritoryUnited States
CityAnaheim, CA


  • Delay monitoring
  • Self-adjusting
  • Variable clock skews

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering


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