Abstract
We propose a self-adjusting pipeline structure to enhance chip performance and robustness considering the effects of process variations. We achieve this by introducing delay sensors to monitor internal timing violations within a pipeline stage and variable clock skew buffers to adjust the timing of the pipeline stage based on the feedback from the delay sensors. Furthermore, we formulate the delay sensor insertion and variable clock skew configuration problem as a stochastic mixed-integer programming problem and propose a simulated-annealing based algorithm to solve it. A comparison between the designs with and without the self-adjusting enhancement reveals that, we are able to improve the average performance of a batch of chips by 9.5%.
Original language | English (US) |
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Title of host publication | Proceedings of the 45th Design Automation Conference, DAC |
Pages | 211-216 |
Number of pages | 6 |
DOIs | |
State | Published - Sep 17 2008 |
Event | 45th Design Automation Conference, DAC - Anaheim, CA, United States Duration: Jun 8 2008 → Jun 13 2008 |
Other
Other | 45th Design Automation Conference, DAC |
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Country/Territory | United States |
City | Anaheim, CA |
Period | 6/8/08 → 6/13/08 |
Keywords
- Delay monitoring
- Self-adjusting
- Variable clock skews
ASJC Scopus subject areas
- Hardware and Architecture
- Control and Systems Engineering