@inproceedings{76d66b0a861f451287689b4a99e119ca,
title = "Automated design of self-adjusting pipelines",
abstract = "We propose a self-adjusting pipeline structure to enhance chip performance and robustness considering the effects of process variations. We achieve this by introducing delay sensors to monitor internal timing violations within a pipeline stage and variable clock skew buffers to adjust the timing of the pipeline stage based on the feedback from the delay sensors. Furthermore, we formulate the delay sensor insertion and variable clock skew configuration problem as a stochastic mixed-integer programming problem and propose a simulated-annealing based algorithm to solve it. A comparison between the designs with and without the self-adjusting enhancement reveals that, we are able to improve the average performance of a batch of chips by 9.5%.",
keywords = "Delay monitoring, Self-adjusting, Variable clock skews",
author = "Jieyi Long and Memik, {Seda Ogrenci}",
year = "2008",
doi = "10.1109/DAC.2008.4555810",
language = "English (US)",
isbn = "9781605581156",
series = "Proceedings - Design Automation Conference",
pages = "211--216",
booktitle = "Proceedings of the 45th Design Automation Conference, DAC",
note = "45th Design Automation Conference, DAC ; Conference date: 08-06-2008 Through 13-06-2008",
}