@inproceedings{c6b46cf208dd4b568c1be10de286c983,
title = "Automated synthesis of pipelined designs on FPGAs for signal and image processing applications described in MATLAB{\textregistered}",
abstract = "We present a compiler that takes high level algorithms described in MATLAB and generates an optimized hardware for an FPGA with external memory. A framework is described to detect and exploit opportunities to pipeline loops in an optimal way. Effectiveness of the framework is demonstrated by synthesizing some image and signal processing applications. Starting from the MATLAB description of the applications, hardware is synthesized that runs on a Xilinx XC4028. The synthesized designs are equivalent to manually optimized designs in performance.",
keywords = "Algorithm design and analysis, Field programmable gate arrays, Finite impulse response filter, Hardware, Image processing, MATLAB, Pipeline processing, Signal design, Signal processing, Signal synthesis",
author = "M. Haldar and A. Nayak and A. Choudhary and P. Banerjee",
note = "Publisher Copyright: {\textcopyright} 2001 IEEE.; Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001 ; Conference date: 30-01-2001 Through 02-02-2001",
year = "2001",
doi = "10.1109/ASPDAC.2001.913382",
language = "English (US)",
series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "645--648",
booktitle = "Proceedings of the ASP-DAC 2001",
address = "United States",
}