Automatic design of area-efficient configurable ASIC cores

Katherine Compton*, Scott Hauck

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

32 Scopus citations

Abstract

Reconfigurable hardware has been shown to provide an efficient compromise between the flexibility of software and the performance of hardware. However, even coarse-grained reconfigurable architectures target the general case and miss optimization opportunities present if characteristics of the desired application set are known. Restricting the structure to support a class or a specific set of algorithms can increase efficiency while still providing flexibility within that set. By generating a custom array for a given computation domain, we explore the design space between an ASIC and an FPGA. However, the manual creation of these customized reprogrammable architectures would be a labor-intensive process, leading to high design costs. Instead, we propose automatic reconfigurable architecture generation specialized to given application sets. This paper discusses configurable ASIC (cASIC) architecture generation that creates hardware on average up to 12.3× smaller than an FPGA solution with embedded multipliers and 2.2× smaller than a standard cell implementation of individual circuits.

Original languageEnglish (US)
Pages (from-to)662-672
Number of pages11
JournalIEEE Transactions on Computers
Volume56
Issue number5
DOIs
StatePublished - May 2007
Externally publishedYes

Keywords

  • Logic design and synthesis
  • Reconfigurable architecture

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

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