TY - JOUR
T1 - Automatic design of reconfigurable domain-specific flexible cores
AU - Compton, Katherine
AU - Hauck, Scott
N1 - Funding Information:
Manuscript received November 24, 2005; revised work was supported in part by grants from the National Science Foundation (NSF), NASA, and Motorola. The work of K. Compton was supported in part by a Cabell Fellowship and by a UPR grant from Motorola. The work of S. Hauck was supported in part by a Sloan Research Fellowship and by an NSF CAREER Award.
PY - 2008/5
Y1 - 2008/5
N2 - Reconfigurable hardware is ideal for use in systems-on-a-chip (SoC), as it provides both hardware-level performance and post-fabrication flexibility. However, any one architecture is rarely equally optimized for all applications. SoCs targeting a specific set of applications can greatly benefit from incorporating customized reconfigurable logic instead of generic field-programmable gate-array (FPGA) logic. Unfortunately, manually designing a domain-specific architecture for every SoC would require significant design time. Instead, this paper discusses our initial efforts towards creating a reconfigurable hardware generator capable of automatically creating flexible, yet domain-specific, designs. Our tests indicate that our generated architectures are more than 5 $\times$ smaller than equivalent FPGA implementations and nearly as area-efficient as standard cell designs. We also use a novel technique employing synthetic circuit generation to demonstrate the flexibility of our architecture generation techniques.
AB - Reconfigurable hardware is ideal for use in systems-on-a-chip (SoC), as it provides both hardware-level performance and post-fabrication flexibility. However, any one architecture is rarely equally optimized for all applications. SoCs targeting a specific set of applications can greatly benefit from incorporating customized reconfigurable logic instead of generic field-programmable gate-array (FPGA) logic. Unfortunately, manually designing a domain-specific architecture for every SoC would require significant design time. Instead, this paper discusses our initial efforts towards creating a reconfigurable hardware generator capable of automatically creating flexible, yet domain-specific, designs. Our tests indicate that our generated architectures are more than 5 $\times$ smaller than equivalent FPGA implementations and nearly as area-efficient as standard cell designs. We also use a novel technique employing synthetic circuit generation to demonstrate the flexibility of our architecture generation techniques.
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U2 - 10.1109/TVLSI.2007.915439
DO - 10.1109/TVLSI.2007.915439
M3 - Article
AN - SCOPUS:42649130684
SN - 1063-8210
VL - 16
SP - 493
EP - 503
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 5
M1 - 4460576
ER -