Abstract
Reconfigurable hardware is ideal for use in systems-on-a-chip (SoC), as it provides both hardware-level performance and post-fabrication flexibility. However, any one architecture is rarely equally optimized for all applications. SoCs targeting a specific set of applications can greatly benefit from incorporating customized reconfigurable logic instead of generic field-programmable gate-array (FPGA) logic. Unfortunately, manually designing a domain-specific architecture for every SoC would require significant design time. Instead, this paper discusses our initial efforts towards creating a reconfigurable hardware generator capable of automatically creating flexible, yet domain-specific, designs. Our tests indicate that our generated architectures are more than 5 $\times$ smaller than equivalent FPGA implementations and nearly as area-efficient as standard cell designs. We also use a novel technique employing synthetic circuit generation to demonstrate the flexibility of our architecture generation techniques.
Original language | English (US) |
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Article number | 4460576 |
Pages (from-to) | 493-503 |
Number of pages | 11 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 16 |
Issue number | 5 |
DOIs | |
State | Published - May 2008 |
Funding
Manuscript received November 24, 2005; revised work was supported in part by grants from the National Science Foundation (NSF), NASA, and Motorola. The work of K. Compton was supported in part by a Cabell Fellowship and by a UPR grant from Motorola. The work of S. Hauck was supported in part by a Sloan Research Fellowship and by an NSF CAREER Award.
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering