TY - GEN
T1 - Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks
AU - Srinath, Shreesha
AU - Compton, Katherine
PY - 2010
Y1 - 2010
N2 - The introduction of asymmetric embedded multiplier blocks in recent Xilinx FPGAs complicates the design of larger multiplier sizes. The two different input bitwidths of the embedded multipliers lead to two different shifting factors for the partial product outputs. This makes even the most straightforward multiplier design less intuitive. In this paper, we present a methodology and set of equations to automatically generate the Verilog for a multiplier using asymmetric embedded multiplier cores. The presented technique also uses intelligent rearrangement of the multiplier block outputs into partial product terms to reduce the overall delay of the circuit. Multipliers created with our generator are faster and use fewer DSP blocks than those created using Xilinx Core Generator or by simply using the '*' operator in Verilog. It also uses fewer LUTs than those created using the '*' operator. Finally, the presented generator can create multipliers larger than possible with Core Generator, and is limited only by the number of available embedded multipliers.
AB - The introduction of asymmetric embedded multiplier blocks in recent Xilinx FPGAs complicates the design of larger multiplier sizes. The two different input bitwidths of the embedded multipliers lead to two different shifting factors for the partial product outputs. This makes even the most straightforward multiplier design less intuitive. In this paper, we present a methodology and set of equations to automatically generate the Verilog for a multiplier using asymmetric embedded multiplier cores. The presented technique also uses intelligent rearrangement of the multiplier block outputs into partial product terms to reduce the overall delay of the circuit. Multipliers created with our generator are faster and use fewer DSP blocks than those created using Xilinx Core Generator or by simply using the '*' operator in Verilog. It also uses fewer LUTs than those created using the '*' operator. Finally, the presented generator can create multipliers larger than possible with Core Generator, and is limited only by the number of available embedded multipliers.
KW - Asymmetric multipliers
KW - Composable multipliers
KW - Multiplier design
UR - http://www.scopus.com/inward/record.url?scp=77951522533&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77951522533&partnerID=8YFLogxK
U2 - 10.1145/1723112.1723123
DO - 10.1145/1723112.1723123
M3 - Conference contribution
AN - SCOPUS:77951522533
SN - 9781605589114
T3 - ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA
SP - 51
EP - 58
BT - FPGA'10 - Proceedings of the 18th ACM SIGDA International Symposium on Field-Programmable Gate Arrays
T2 - 18th ACM SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA'10
Y2 - 21 February 2010 through 23 February 2010
ER -