Automatic translation of software binaries onto FPGAs

Gaurav Mittal*, David C. Zaretsky, Xiaoyong Tang, P. Banerjee

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

24 Scopus citations


The introduction of advanced FPGA architectures, with built-in DSP support, has given DSP designers a new hardware alternative. By exploiting its inherent parallelism, it is expected that FPGAs can outperform DSP processors. This paper describes the process and considerations for automatically translating binaries targeted for general DSP processors into Register Transfer Level (RTL) VHDL or Verilog code to be mapped onto commercial FPGAs. The Texas Instruments C6000 DSP processor architecture is chosen as the DSP processor platform, and the Xilinx Virtex II as a target FPGA. Various optimizations are discussed, including data dependency analysis, procedure extraction, induction variable analysis, memory optimizations, and scheduling. Experimental results on resource usage and performance are shown for ten software binary benchmarks. Results show performance gains of 3-20X in the FPGA designs over that of the DSP processors in terms of reductions of execution cycles.

Original languageEnglish (US)
Pages (from-to)389-394
Number of pages6
JournalProceedings - Design Automation Conference
StatePublished - 2004
EventProceedings of the 41st Design Automation Conference - San Diego, CA, United States
Duration: Jun 7 2004Jun 11 2004


  • Binary translation
  • Compiler
  • Decompilation
  • Hardware-software co-design
  • Reconfigurable computing

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering


Dive into the research topics of 'Automatic translation of software binaries onto FPGAs'. Together they form a unique fingerprint.

Cite this