Abstract
Because of the high cost of communication between processors, compilers that parallelize loops automatically have been forced to skip a large class of loops that are both critical to performance and rich in latent parallelism. HELIX-RC is a compiler/microprocessor co-design that opens those loops to parallelization by decoupling communication from thread execution in conventional multicore architecures. Simulations of HELIX-RC, applied to a processor with 16 Intel Atom-like cores, show an average of 6.85× performance speedup for six SPEC CINT2000 benchmarks.
Original language | English (US) |
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Pages (from-to) | 88-97 |
Number of pages | 10 |
Journal | Communications of the ACM |
Volume | 60 |
Issue number | 12 |
DOIs | |
State | Published - Dec 2017 |
ASJC Scopus subject areas
- Computer Science(all)