Balanced scheduling and operation chaining in high-level synthesis for FPGA designs

David C. Zaretsky*, Gaurav Mittal, Robert P. Dick, Prith Banerjee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations

Abstract

In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced scheduling routine that uniformly distributes operations across states to reduce critical timing paths in the absence of accurate functional unit delay models. On average, results show improvements in frequency and run times for balanced scheduling over ASAP, ALAP, and force-directed scheduling. Additionally, we provide a methodology for precision-based delay modeling of operations. We present a balanced chaining routine that, given a target frequency, uses this modeling technique to reduce the number of clock cycles in the design. Results show approximately 20% improvement on average in run times when incorporating our balanced chaining routine with scheduling. Applying balanced chaining in a high-level synthesis tool allowed performance improvements between 8-29× for large, complex applications. Our method for modeling operation delays is shown to be accurate in estimating delays for operation chaining during high-level synthesis.

Original languageEnglish (US)
Title of host publicationProceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007
Pages595-601
Number of pages7
DOIs
StatePublished - 2007
Externally publishedYes
Event8th International Symposium on Quality Electronic Design, ISQED 2007 - San Jose, CA, United States
Duration: Mar 26 2007Mar 28 2007

Publication series

NameProceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007

Conference

Conference8th International Symposium on Quality Electronic Design, ISQED 2007
Country/TerritoryUnited States
CitySan Jose, CA
Period3/26/073/28/07

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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