Binning optimization based on SSTA for transparently-latched circuits

Min Gong, Hai Zhou, Jun Tao, Xuan Zeng*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transparent latches are widely used. In this paper, we formulate and solve the binning optimization problem that decides the bin boundaries and their testing order to maximize the benefit (considering the test cost) for a transparentlylatched circuit. The problem is decomposed into three sub-problems which are solved sequentially. First, to compute the clock period distribution of the transparently-latched circuit, a sample-based SSTA approach is developed which is based on the generalized stochastic collocation method (gSCM) with Sparse Grid technique. The minimal clock period on each sample point is found by solving a minimal cycle ratio problem in the constraint graph. Second, a greedy algorithm is proposed to maximize the sales profit by iteratively assigning each boundary to its optimal position. Then, an optimal algorithm of O(n log n) runtime is used to generate the optimal testing order of bin boundaries to minimize the test cost, based on alphabetic tree. Experiments on all the ISCAS'89 sequential benchmarks with 65-nm technology show 6.69% profit improvement and 14.00% cost reduction in average. The results also demonstrate that the proposed SSTA method achieves an error of 0.70% and speedup of 110X in average compared with the Monte Carlo simulation.

Original languageEnglish (US)
Title of host publicationProceedings of the 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers, ICCAD 2009
Pages328-335
Number of pages8
StatePublished - Dec 1 2009
Event2009 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2009 - San Jose, CA, United States
Duration: Nov 2 2009Nov 5 2009

Other

Other2009 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2009
CountryUnited States
CitySan Jose, CA
Period11/2/0911/5/09

Keywords

  • Binning optimization
  • Latched circuits
  • SSTA

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Computer Science Applications
  • Software

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