Buffer minimization in pass transistor logic

Hai Zhou*, Adnan Aziz

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

With the shrinking feature sizes and increasing transistor counts on chips, the push for higher speed and lower power makes it necessary to look for alternative design styles which offer better performance characteristics than static CMOS. Among them, pass transistor logic (PTL) circuits give great promise. Since the delay in a pass-transistor chain is quadratically proportional to the number of stages, and a signal may degenerate when passing through a transistor, buffers are necessary to guarantee performance and restore signal strength in PTL circuits. In this paper, we first analyze the effects of buffer insertion on a circuit and give the sufficient and necessary condition for safe buffer insertion. Then the buffer minimization problem is formulated, which asks for a minimum number of buffers to make sure that no path has length longer than a given upper bound. Although NP-hard in general, we show that, when buffers are required on multiple fan-outs, it can be solved linearly. We also consider the case when buffers are inverters, where phase assignment need to be done with buffer insertion. Experiments are done on MCNC logic synthesis and optimization benchmarks; compared with a level-by-level insertion, a large number of buffers are saved.

Original languageEnglish (US)
Title of host publicationProceedings of the International Symposium on Physical Design
PublisherACM
Pages105-110
Number of pages6
StatePublished - Jan 1 2000
EventISPD-2000: International Symposium on Physical Design - San Diego, CA, USA
Duration: Apr 9 2000Apr 12 2000

Other

OtherISPD-2000: International Symposium on Physical Design
CitySan Diego, CA, USA
Period4/9/004/12/00

ASJC Scopus subject areas

  • Engineering(all)

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