Buffer minimization in pass transistor logic

Hai Zhou*, Adnan Aziz

*Corresponding author for this work

Research output: Contribution to journalArticle

5 Scopus citations

Abstract

With shrinking feature sizes and increasing transistor counts on chips, demands for higher speed and lower power make it necessary to look for alternative design styles that offer better performance than static complementary metal-oxide-semiconductors. Among them, pass transistor logic (PTL) is of great promise. Since delay in a transistor chain is quadratically proportional to the number of transistors and a signal may degenerate passing through a transistor, buffers are necessary to guarantee performance and restore signal strength in PTL circuits. In this paper, we first analyze effects of buffer insertion on a circuit and give a sufficient and necessary condition for safe buffer insertion. Then, a buffer minimization problem is formulated. Although it is NP-hard in general, it can be solved linearly when buffers are required on multifan-out nodes. We also consider the case when buffers are inverters, where phase assignment needs to be done with buffer insertion.

Original languageEnglish (US)
Pages (from-to)693-697
Number of pages5
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume20
Issue number5
DOIs
StatePublished - May 2001

Keywords

  • Buffers
  • Pass transistor logic performance

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Buffer minimization in pass transistor logic'. Together they form a unique fingerprint.

  • Cite this