CDF level 2 trigger upgrade

K. Anikeev; M. Bogdan; R. Demaat; W. Fedorko; H. Frisch; K. Hahn; M. Hakala; P. Keener; Y. Kim; J. Kroll; S. Kwang; J. Lewis; C. Lin; T. Liu; F. Marjamaa; T. Mansikkala; C. Neu; S. Pitkanen; B. Reisert; V. Rusu; H. Sanders; M. Shochet; H. Stabenau; R. Vanberg; P. Wilson; D. Whiteson; P. Wittich

doi:10.1109/TNS.2006.871782

CDF level 2 trigger upgrade

K. Anikeev, M. Bogdan, R. Demaat, W. Fedorko, H. Frisch, K. Hahn, M. Hakala, P. Keener, Y. Kim, J. Kroll, S. Kwang, J. Lewis, C. Lin, T. Liu, F. Marjamaa, T. Mansikkala, C. Neu, S. Pitkanen, B. Reisert, V. RusuH. Sanders, M. Shochet, H. Stabenau, R. Vanberg, P. Wilson, D. Whiteson, P. Wittich

Research output: Contribution to journal › Article › peer-review

24 Scopus citations

Abstract

We describe the new CDF Level 2 Trigger, which was commissioned during Spring 2005. The upgrade was necessitated by several factors that included increased bandwidth requirements, in view of the growing instantaneous luminosity of the Tevatron, and the need for a more robust system, since the older system was reaching the limits of maintainability. The challenges in designing the new system were interfacing with many different upstream detector subsystems, processing larger volumes of data at higher speed, and minimizing the impact on running the CDF experiment during the system commissioning phase. To meet these challenges, the new system was designed around a general purpose motherboard, the PULSAR, which is instrumented with powerful FPGAs and modern SRAMs, and which uses mezzanine cards to interface with upstream detector components and an industry standard data link (S-LINK) within the system.

Original language	English (US)
Pages (from-to)	653-658
Number of pages	6
Journal	IEEE Transactions on Nuclear Science
Volume	53
Issue number	2
DOIs	https://doi.org/10.1109/TNS.2006.871782
State	Published - Apr 2006
Externally published	Yes

Keywords

FPGA based hardware
Real-time systems
Trigger

ASJC Scopus subject areas

Nuclear and High Energy Physics
Nuclear Energy and Engineering
Electrical and Electronic Engineering

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10.1109/TNS.2006.871782

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@article{f1ae2665e3f54fdc94382bff85a32635,

title = "CDF level 2 trigger upgrade",

abstract = "We describe the new CDF Level 2 Trigger, which was commissioned during Spring 2005. The upgrade was necessitated by several factors that included increased bandwidth requirements, in view of the growing instantaneous luminosity of the Tevatron, and the need for a more robust system, since the older system was reaching the limits of maintainability. The challenges in designing the new system were interfacing with many different upstream detector subsystems, processing larger volumes of data at higher speed, and minimizing the impact on running the CDF experiment during the system commissioning phase. To meet these challenges, the new system was designed around a general purpose motherboard, the PULSAR, which is instrumented with powerful FPGAs and modern SRAMs, and which uses mezzanine cards to interface with upstream detector components and an industry standard data link (S-LINK) within the system.",

keywords = "FPGA based hardware, Real-time systems, Trigger",

author = "K. Anikeev and M. Bogdan and R. Demaat and W. Fedorko and H. Frisch and K. Hahn and M. Hakala and P. Keener and Y. Kim and J. Kroll and S. Kwang and J. Lewis and C. Lin and T. Liu and F. Marjamaa and T. Mansikkala and C. Neu and S. Pitkanen and B. Reisert and V. Rusu and H. Sanders and M. Shochet and H. Stabenau and R. Vanberg and P. Wilson and D. Whiteson and P. Wittich",

year = "2006",

month = apr,

doi = "10.1109/TNS.2006.871782",

language = "English (US)",

volume = "53",

pages = "653--658",

journal = "IEEE Transactions on Nuclear Science",

issn = "0018-9499",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "2",

}

Anikeev, K, Bogdan, M, Demaat, R, Fedorko, W, Frisch, H, Hahn, K, Hakala, M, Keener, P, Kim, Y, Kroll, J, Kwang, S, Lewis, J, Lin, C, Liu, T, Marjamaa, F, Mansikkala, T, Neu, C, Pitkanen, S, Reisert, B, Rusu, V, Sanders, H, Shochet, M, Stabenau, H, Vanberg, R, Wilson, P, Whiteson, D & Wittich, P 2006, 'CDF level 2 trigger upgrade', IEEE Transactions on Nuclear Science, vol. 53, no. 2, pp. 653-658. https://doi.org/10.1109/TNS.2006.871782

TY - JOUR

T1 - CDF level 2 trigger upgrade

AU - Anikeev, K.

AU - Bogdan, M.

AU - Demaat, R.

AU - Fedorko, W.

AU - Frisch, H.

AU - Hahn, K.

AU - Hakala, M.

AU - Keener, P.

AU - Kim, Y.

AU - Kroll, J.

AU - Kwang, S.

AU - Lewis, J.

AU - Lin, C.

AU - Liu, T.

AU - Marjamaa, F.

AU - Mansikkala, T.

AU - Neu, C.

AU - Pitkanen, S.

AU - Reisert, B.

AU - Rusu, V.

AU - Sanders, H.

AU - Shochet, M.

AU - Stabenau, H.

AU - Vanberg, R.

AU - Wilson, P.

AU - Whiteson, D.

AU - Wittich, P.

PY - 2006/4

Y1 - 2006/4

N2 - We describe the new CDF Level 2 Trigger, which was commissioned during Spring 2005. The upgrade was necessitated by several factors that included increased bandwidth requirements, in view of the growing instantaneous luminosity of the Tevatron, and the need for a more robust system, since the older system was reaching the limits of maintainability. The challenges in designing the new system were interfacing with many different upstream detector subsystems, processing larger volumes of data at higher speed, and minimizing the impact on running the CDF experiment during the system commissioning phase. To meet these challenges, the new system was designed around a general purpose motherboard, the PULSAR, which is instrumented with powerful FPGAs and modern SRAMs, and which uses mezzanine cards to interface with upstream detector components and an industry standard data link (S-LINK) within the system.

AB - We describe the new CDF Level 2 Trigger, which was commissioned during Spring 2005. The upgrade was necessitated by several factors that included increased bandwidth requirements, in view of the growing instantaneous luminosity of the Tevatron, and the need for a more robust system, since the older system was reaching the limits of maintainability. The challenges in designing the new system were interfacing with many different upstream detector subsystems, processing larger volumes of data at higher speed, and minimizing the impact on running the CDF experiment during the system commissioning phase. To meet these challenges, the new system was designed around a general purpose motherboard, the PULSAR, which is instrumented with powerful FPGAs and modern SRAMs, and which uses mezzanine cards to interface with upstream detector components and an industry standard data link (S-LINK) within the system.

KW - FPGA based hardware

KW - Real-time systems

KW - Trigger

UR - http://www.scopus.com/inward/record.url?scp=33646435312&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33646435312&partnerID=8YFLogxK

U2 - 10.1109/TNS.2006.871782

DO - 10.1109/TNS.2006.871782

M3 - Article

AN - SCOPUS:33646435312

SN - 0018-9499

VL - 53

SP - 653

EP - 658

JO - IEEE Transactions on Nuclear Science

JF - IEEE Transactions on Nuclear Science

IS - 2

ER -

CDF level 2 trigger upgrade

Abstract

Keywords

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