Cell library characterization at low voltage using non-linear operating point analysis of local variations

Rahul Rithe; Sharon Chou; Jie Gu; Alice Wang; Satyendra Datla; Gordon Gammie; Dennis Buss; Anantha Chandrakasan

doi:10.1109/VLSID.2011.43

Cell library characterization at low voltage using non-linear operating point analysis of local variations

Rahul Rithe^*, Sharon Chou, Jie Gu, Alice Wang, Satyendra Datla, Gordon Gammie, Dennis Buss, Anantha Chandrakasan

^*Corresponding author for this work

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

When CMOS is operated at a supply voltage of 0.5V and below, Random Dopant Fluctuations (RDFs) result in a stochastic component of logic delay that can be comparable to the nominal delay. Moreover, the Probability Density Function (PDF) of this stochastic delay can be highly non-Gaussian. The Non-Linear, Operating Point Analysis of Local Variations (NLOPALV) technique has been shown to be accurate and computationally efficient in simulating any point on the delay PDF of a logic Timing Path (TP). This paper applies the NLOPALV approach to characterizing the stochastic delay of logic cells. NLOPALV theory is presented, and NLOPALV is used to characterize a cell library designed in 28 nm CMOS. NLOPALV is accurate to within 5% compared to SPICE-based Monte Carlo analysis.

Original language	English (US)
Title of host publication	Proceedings - 24th International Conference on VLSI Design, VLSI Design 2011, Held Jointly with 10th International Conference on Embedded Systems
Pages	112-117
Number of pages	6
DOIs	https://doi.org/10.1109/VLSID.2011.43
State	Published - 2011
Event	24th International Conference on VLSI Design, VLSI Design 2011, Held Jointly with 10th International Conference on Embedded Systems - Chennai, India Duration: Jan 2 2011 → Jan 7 2011

Publication series

Name	Proceedings of the IEEE International Conference on VLSI Design
ISSN (Print)	1063-9667

Other

Other	24th International Conference on VLSI Design, VLSI Design 2011, Held Jointly with 10th International Conference on Embedded Systems
Country/Territory	India
City	Chennai
Period	1/2/11 → 1/7/11

Keywords

Local variations
Low voltage
Timing analysis

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/VLSID.2011.43

Cite this

Rithe, R., Chou, S., Gu, J., Wang, A., Datla, S., Gammie, G., Buss, D., & Chandrakasan, A. (2011). Cell library characterization at low voltage using non-linear operating point analysis of local variations. In Proceedings - 24th International Conference on VLSI Design, VLSI Design 2011, Held Jointly with 10th International Conference on Embedded Systems (pp. 112-117). Article 5718787 (Proceedings of the IEEE International Conference on VLSI Design). https://doi.org/10.1109/VLSID.2011.43

Rithe, Rahul ; Chou, Sharon ; Gu, Jie et al. / Cell library characterization at low voltage using non-linear operating point analysis of local variations. Proceedings - 24th International Conference on VLSI Design, VLSI Design 2011, Held Jointly with 10th International Conference on Embedded Systems. 2011. pp. 112-117 (Proceedings of the IEEE International Conference on VLSI Design).

@inproceedings{451c62ccbe414121a2406eec209d76f6,

title = "Cell library characterization at low voltage using non-linear operating point analysis of local variations",

abstract = "When CMOS is operated at a supply voltage of 0.5V and below, Random Dopant Fluctuations (RDFs) result in a stochastic component of logic delay that can be comparable to the nominal delay. Moreover, the Probability Density Function (PDF) of this stochastic delay can be highly non-Gaussian. The Non-Linear, Operating Point Analysis of Local Variations (NLOPALV) technique has been shown to be accurate and computationally efficient in simulating any point on the delay PDF of a logic Timing Path (TP). This paper applies the NLOPALV approach to characterizing the stochastic delay of logic cells. NLOPALV theory is presented, and NLOPALV is used to characterize a cell library designed in 28 nm CMOS. NLOPALV is accurate to within 5% compared to SPICE-based Monte Carlo analysis.",

keywords = "Local variations, Low voltage, Timing analysis",

author = "Rahul Rithe and Sharon Chou and Jie Gu and Alice Wang and Satyendra Datla and Gordon Gammie and Dennis Buss and Anantha Chandrakasan",

year = "2011",

doi = "10.1109/VLSID.2011.43",

language = "English (US)",

isbn = "9780769543482",

series = "Proceedings of the IEEE International Conference on VLSI Design",

pages = "112--117",

booktitle = "Proceedings - 24th International Conference on VLSI Design, VLSI Design 2011, Held Jointly with 10th International Conference on Embedded Systems",

note = "24th International Conference on VLSI Design, VLSI Design 2011, Held Jointly with 10th International Conference on Embedded Systems ; Conference date: 02-01-2011 Through 07-01-2011",

}

Rithe, R, Chou, S, Gu, J, Wang, A, Datla, S, Gammie, G, Buss, D & Chandrakasan, A 2011, Cell library characterization at low voltage using non-linear operating point analysis of local variations. in Proceedings - 24th International Conference on VLSI Design, VLSI Design 2011, Held Jointly with 10th International Conference on Embedded Systems., 5718787, Proceedings of the IEEE International Conference on VLSI Design, pp. 112-117, 24th International Conference on VLSI Design, VLSI Design 2011, Held Jointly with 10th International Conference on Embedded Systems, Chennai, India, 1/2/11. https://doi.org/10.1109/VLSID.2011.43

Cell library characterization at low voltage using non-linear operating point analysis of local variations. / Rithe, Rahul; Chou, Sharon; Gu, Jie et al.
Proceedings - 24th International Conference on VLSI Design, VLSI Design 2011, Held Jointly with 10th International Conference on Embedded Systems. 2011. p. 112-117 5718787 (Proceedings of the IEEE International Conference on VLSI Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Cell library characterization at low voltage using non-linear operating point analysis of local variations

AU - Rithe, Rahul

AU - Chou, Sharon

AU - Gu, Jie

AU - Wang, Alice

AU - Datla, Satyendra

AU - Gammie, Gordon

AU - Buss, Dennis

AU - Chandrakasan, Anantha

PY - 2011

Y1 - 2011

N2 - When CMOS is operated at a supply voltage of 0.5V and below, Random Dopant Fluctuations (RDFs) result in a stochastic component of logic delay that can be comparable to the nominal delay. Moreover, the Probability Density Function (PDF) of this stochastic delay can be highly non-Gaussian. The Non-Linear, Operating Point Analysis of Local Variations (NLOPALV) technique has been shown to be accurate and computationally efficient in simulating any point on the delay PDF of a logic Timing Path (TP). This paper applies the NLOPALV approach to characterizing the stochastic delay of logic cells. NLOPALV theory is presented, and NLOPALV is used to characterize a cell library designed in 28 nm CMOS. NLOPALV is accurate to within 5% compared to SPICE-based Monte Carlo analysis.

AB - When CMOS is operated at a supply voltage of 0.5V and below, Random Dopant Fluctuations (RDFs) result in a stochastic component of logic delay that can be comparable to the nominal delay. Moreover, the Probability Density Function (PDF) of this stochastic delay can be highly non-Gaussian. The Non-Linear, Operating Point Analysis of Local Variations (NLOPALV) technique has been shown to be accurate and computationally efficient in simulating any point on the delay PDF of a logic Timing Path (TP). This paper applies the NLOPALV approach to characterizing the stochastic delay of logic cells. NLOPALV theory is presented, and NLOPALV is used to characterize a cell library designed in 28 nm CMOS. NLOPALV is accurate to within 5% compared to SPICE-based Monte Carlo analysis.

KW - Local variations

KW - Low voltage

KW - Timing analysis

UR - http://www.scopus.com/inward/record.url?scp=79952823480&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79952823480&partnerID=8YFLogxK

U2 - 10.1109/VLSID.2011.43

DO - 10.1109/VLSID.2011.43

M3 - Conference contribution

AN - SCOPUS:79952823480

SN - 9780769543482

T3 - Proceedings of the IEEE International Conference on VLSI Design

SP - 112

EP - 117

BT - Proceedings - 24th International Conference on VLSI Design, VLSI Design 2011, Held Jointly with 10th International Conference on Embedded Systems

T2 - 24th International Conference on VLSI Design, VLSI Design 2011, Held Jointly with 10th International Conference on Embedded Systems

Y2 - 2 January 2011 through 7 January 2011

ER -

Rithe R, Chou S, Gu J, Wang A, Datla S, Gammie G et al. Cell library characterization at low voltage using non-linear operating point analysis of local variations. In Proceedings - 24th International Conference on VLSI Design, VLSI Design 2011, Held Jointly with 10th International Conference on Embedded Systems. 2011. p. 112-117. 5718787. (Proceedings of the IEEE International Conference on VLSI Design). doi: 10.1109/VLSID.2011.43

Cell library characterization at low voltage using non-linear operating point analysis of local variations

Abstract

Publication series

Other

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this