Circuit design and modeling techniques for enhancing the clock-data compensation effect under resonant supply noise

Recent publications have shown that clock jitter can improve timing margin through the compensation effect between the clock cycle and the datapath delay under the influence of resonant supply noise. This paper presents a comprehensive study of this beneficial clock-data compensation effect including an analysis of its dependency on various design parameters and a new phase-shifted clock buffer design that can enhance the effect. Measurement result from a 1.2 V, 65 nm test chip shows an 8-27% increase in the maximum operating frequency while saving 85% of the clock buffer area compared to prior art. An accurate timing model is derived to estimate the beneficial jitter effect.