Clock Schedule Verification with Crosstalk

Hai Zhou

doi:10.1145/589411.589428

Clock Schedule Verification with Crosstalk

Hai Zhou^*

^*Corresponding author for this work

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

Delay variation due to crosstalk has made timing analysis a hard problem. In sequential circuits with transparent latches, crosstalk makes the clock schedule verification even harder. In this paper, we point out a false negative problem in current clock schedule verification techniques and propose a new approach based on switching windows. In this approach, coupling delay calculations are naturally combined with latch iterations. A novel algorithm is given for clock schedule verification in the presence of crosstalk and primary experiments show promising results.

Original language	English (US)
Title of host publication	ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems
Publisher	Association for Computing Machinery (ACM)
Pages	78-83
Number of pages	6
ISBN (Print)	1581135262, 9781581135268
DOIs	https://doi.org/10.1145/589411.589428
State	Published - 2002
Event	ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems - Monterey, CA, United States Duration: Dec 2 2002 → Dec 3 2002

Publication series

Name	ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems

Other

Other	ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems
Country/Territory	United States
City	Monterey, CA
Period	12/2/02 → 12/3/02

Keywords

Clock Schedule
Coupling
Delay
Verification

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1145/589411.589428

Cite this

@inproceedings{ed023fad748e4400b79bc41572b1bcc5,

title = "Clock Schedule Verification with Crosstalk",

abstract = "Delay variation due to crosstalk has made timing analysis a hard problem. In sequential circuits with transparent latches, crosstalk makes the clock schedule verification even harder. In this paper, we point out a false negative problem in current clock schedule verification techniques and propose a new approach based on switching windows. In this approach, coupling delay calculations are naturally combined with latch iterations. A novel algorithm is given for clock schedule verification in the presence of crosstalk and primary experiments show promising results.",

keywords = "Clock Schedule, Coupling, Delay, Verification",

author = "Hai Zhou",

year = "2002",

doi = "10.1145/589411.589428",

language = "English (US)",

isbn = "1581135262",

series = "ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems",

publisher = "Association for Computing Machinery (ACM)",

pages = "78--83",

booktitle = "ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems",

address = "United States",

note = "ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems ; Conference date: 02-12-2002 Through 03-12-2002",

}

Zhou, H 2002, Clock Schedule Verification with Crosstalk. in ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Association for Computing Machinery (ACM), pp. 78-83, ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Monterey, CA, United States, 12/2/02. https://doi.org/10.1145/589411.589428

Clock Schedule Verification with Crosstalk. / Zhou, Hai.
ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems. Association for Computing Machinery (ACM), 2002. p. 78-83 (ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Clock Schedule Verification with Crosstalk

AU - Zhou, Hai

PY - 2002

Y1 - 2002

N2 - Delay variation due to crosstalk has made timing analysis a hard problem. In sequential circuits with transparent latches, crosstalk makes the clock schedule verification even harder. In this paper, we point out a false negative problem in current clock schedule verification techniques and propose a new approach based on switching windows. In this approach, coupling delay calculations are naturally combined with latch iterations. A novel algorithm is given for clock schedule verification in the presence of crosstalk and primary experiments show promising results.

AB - Delay variation due to crosstalk has made timing analysis a hard problem. In sequential circuits with transparent latches, crosstalk makes the clock schedule verification even harder. In this paper, we point out a false negative problem in current clock schedule verification techniques and propose a new approach based on switching windows. In this approach, coupling delay calculations are naturally combined with latch iterations. A novel algorithm is given for clock schedule verification in the presence of crosstalk and primary experiments show promising results.

KW - Clock Schedule

KW - Coupling

KW - Delay

KW - Verification

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DO - 10.1145/589411.589428

M3 - Conference contribution

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T3 - ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems

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BT - ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems

PB - Association for Computing Machinery (ACM)

T2 - ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems

Y2 - 2 December 2002 through 3 December 2002

ER -

Clock Schedule Verification with Crosstalk

Abstract

Publication series

Other

Keywords

ASJC Scopus subject areas

Access to Document

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