Clock skew scheduling with delay padding for prescribed skew domains

Chuan Lin*, Hai Zhou

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

31 Scopus citations

Abstract

Clock skew scheduling is a technique that intentionally introduces skews to memory elements to improve the performance of a sequential circuit. It was shown in [21] that the full optimization potential of clock skew scheduling can be reliably implemented using a few skew domains. In this paper we present an optimal skew scheduling algorithm for sequential circuits with flip-flops. Given a finite set of prescribed skew domains, the algorithm finds a domain assignment for each flip-flop such that the clock period is minimized with possible delay padding. Experimental results validate the efficiency of our algorithm and show 17% improvement on average in clock period.

Original languageEnglish (US)
Title of host publicationProceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
Pages541-546
Number of pages6
DOIs
StatePublished - Dec 1 2007
EventASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 - Yokohama, Japan
Duration: Jan 23 2007Jan 27 2007

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

OtherASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
CountryJapan
CityYokohama
Period1/23/071/27/07

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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