Clustering for processing rate optimization

Chuan Lin*, Jia Wang, Hai Zhou

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level may have timing closure problems at post-layout stages due to the emergence of multiple-clock-period interconnects. Consequently, a tradeoff between clock frequency and throughput may be needed to meet the design requirements. In this paper, we find that the processing rate, defined as the product of frequency and throughput, of a sequential system is upper bounded by the reciprocal of its maximum cycle ratio, which is only dependent on the clustering. We formulate the problem of processing rate optimization as seeking an optimal clustering with the minimal maximum-cycle-ratio in a general graph, and present an iterative algorithm to solve it. Experimental results validate the efficiency of our algorithm.

Original languageEnglish (US)
Pages (from-to)1264-1275
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume14
Issue number11
DOIs
StatePublished - Nov 2006

Keywords

  • Algorithms
  • Circuit optimization
  • Clustering methods
  • Design automation
  • Integrated circuit interconnections

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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