Abstract
Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level may have timing closure problems at post-layout stages due to the emergence of multiple-clock-period interconnects. Consequently, a tradeoff between clock frequency and throughput may be needed to meet the design requirements. In this paper, we find that the processing rate, defined as the product of frequency and throughput, of a sequential system is upper bounded by the reciprocal of its maximum cycle ratio, which is only dependent on the clustering. We formulate the problem of processing rate optimization as seeking an optimal clustering with the minimal maximum-cycle-ratio in a general graph, and present an iterative algorithm to solve it. Experimental results validate the efficiency of our algorithm.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 1264-1275 |
| Number of pages | 12 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 14 |
| Issue number | 11 |
| DOIs | |
| State | Published - Nov 2006 |
Funding
Manuscript received December 30, 2005; revised March 24, 2006. This work was supported by the National Science Foundation under Grant CCR-0238484. C. Lin is with the Logic Synthesis Group, Magma Design Automation Inc., Santa Clara, CA 95054 USA. J. Wang and H. Zhou are with the Electrical Engineering and Computer Science Department, Northwestern University, Evanston, IL 60208 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/TVLSI.2006.886399
Keywords
- Algorithms
- Circuit optimization
- Clustering methods
- Design automation
- Integrated circuit interconnections
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering