Cocoa

Synergistic cache compression and error correction in capacity sensitive last level caches

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Voltage scaling is one of the most effective techniques to provide power savings on a chip-wide basis. However, reducing supply voltage in the presence of process variation introduces significant reliability challenges for large SRAM arrays. The rapid decrease in SRAM reliability at low voltages determines a minimum operating voltage (Vccmin). This places a floor on the power consumption of the entire processor. Therefore, processors must either stay at high voltages where the low defect densities are tolerable or work at low voltages with existing fault tolerance schemes which sacrifice a large fraction of the cache capacity for improved reliability. In the latter case, processors could obtain significant energy reduction from the aggressive voltage scaling. However, the decrease in the last-level cache (LLC) capacity may have a detrimental impact on both performance and energy consumption. In this work, we propose a novel technique to enable reliable low voltage operation and preserve capacity for LLCs. In this technique, synergistic cache compression and error correction (Cocoa), we apply compression to LLCs to harvest additional capacity to store ECC check bits. In addition, we introduce a new ECC scheme to minimize the space overhead of ECC. In particular, we employ variable strength ECC on a per-segment basis. In the common case, segments with zero or one bit failures are protected by weak ECC. Few segments with multi-bit failures are protected by strong ECC. Our evaluation for a 2MB 8-way set associative L3 cache shows that the proposed schemes can guarantee reliable cache operation beyond 400mV. Compared to a conventional cache with a Vccmin of 810mV, our schemes reduce the system energy per instruction (Core+L3+DRAM) by 54.5%. Furthermore, we achieve 0.8% higher performance even than a fault-free cache when operating at 400mV. We also demonstrate that our energy benefits remain robust across a broad range of cache sizes and supply voltages.

Original languageEnglish (US)
Title of host publicationMEMSYS 2018 - Proceedings of the International Symposium on Memory Systems
PublisherAssociation for Computing Machinery
ISBN (Electronic)9781450364751
DOIs
StatePublished - Oct 1 2018
Event2018 International Symposium on Memory Systems, MEMSYS 2018 - Alexandria, United States
Duration: Oct 1 2018Oct 4 2018

Other

Other2018 International Symposium on Memory Systems, MEMSYS 2018
CountryUnited States
CityAlexandria
Period10/1/1810/4/18

Fingerprint

Cocoa
Error correction
Electric potential
Static random access storage
Dynamic random access storage
Defect density
Fault tolerance
Electric power utilization
Energy utilization

Keywords

  • Cache compression
  • Error correcting code
  • Fault tolerance caches
  • Voltage scaling

ASJC Scopus subject areas

  • Human-Computer Interaction
  • Computer Networks and Communications
  • Computer Vision and Pattern Recognition
  • Software

Cite this

Yan, C., & Joseph, R. E. (2018). Cocoa: Synergistic cache compression and error correction in capacity sensitive last level caches. In MEMSYS 2018 - Proceedings of the International Symposium on Memory Systems Association for Computing Machinery. https://doi.org/10.1145/3240302.3240304
Yan, Chao ; Joseph, Russell E. / Cocoa : Synergistic cache compression and error correction in capacity sensitive last level caches. MEMSYS 2018 - Proceedings of the International Symposium on Memory Systems. Association for Computing Machinery, 2018.
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title = "Cocoa: Synergistic cache compression and error correction in capacity sensitive last level caches",
abstract = "Voltage scaling is one of the most effective techniques to provide power savings on a chip-wide basis. However, reducing supply voltage in the presence of process variation introduces significant reliability challenges for large SRAM arrays. The rapid decrease in SRAM reliability at low voltages determines a minimum operating voltage (Vccmin). This places a floor on the power consumption of the entire processor. Therefore, processors must either stay at high voltages where the low defect densities are tolerable or work at low voltages with existing fault tolerance schemes which sacrifice a large fraction of the cache capacity for improved reliability. In the latter case, processors could obtain significant energy reduction from the aggressive voltage scaling. However, the decrease in the last-level cache (LLC) capacity may have a detrimental impact on both performance and energy consumption. In this work, we propose a novel technique to enable reliable low voltage operation and preserve capacity for LLCs. In this technique, synergistic cache compression and error correction (Cocoa), we apply compression to LLCs to harvest additional capacity to store ECC check bits. In addition, we introduce a new ECC scheme to minimize the space overhead of ECC. In particular, we employ variable strength ECC on a per-segment basis. In the common case, segments with zero or one bit failures are protected by weak ECC. Few segments with multi-bit failures are protected by strong ECC. Our evaluation for a 2MB 8-way set associative L3 cache shows that the proposed schemes can guarantee reliable cache operation beyond 400mV. Compared to a conventional cache with a Vccmin of 810mV, our schemes reduce the system energy per instruction (Core+L3+DRAM) by 54.5{\%}. Furthermore, we achieve 0.8{\%} higher performance even than a fault-free cache when operating at 400mV. We also demonstrate that our energy benefits remain robust across a broad range of cache sizes and supply voltages.",
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Yan, C & Joseph, RE 2018, Cocoa: Synergistic cache compression and error correction in capacity sensitive last level caches. in MEMSYS 2018 - Proceedings of the International Symposium on Memory Systems. Association for Computing Machinery, 2018 International Symposium on Memory Systems, MEMSYS 2018, Alexandria, United States, 10/1/18. https://doi.org/10.1145/3240302.3240304

Cocoa : Synergistic cache compression and error correction in capacity sensitive last level caches. / Yan, Chao; Joseph, Russell E.

MEMSYS 2018 - Proceedings of the International Symposium on Memory Systems. Association for Computing Machinery, 2018.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Cocoa

T2 - Synergistic cache compression and error correction in capacity sensitive last level caches

AU - Yan, Chao

AU - Joseph, Russell E

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N2 - Voltage scaling is one of the most effective techniques to provide power savings on a chip-wide basis. However, reducing supply voltage in the presence of process variation introduces significant reliability challenges for large SRAM arrays. The rapid decrease in SRAM reliability at low voltages determines a minimum operating voltage (Vccmin). This places a floor on the power consumption of the entire processor. Therefore, processors must either stay at high voltages where the low defect densities are tolerable or work at low voltages with existing fault tolerance schemes which sacrifice a large fraction of the cache capacity for improved reliability. In the latter case, processors could obtain significant energy reduction from the aggressive voltage scaling. However, the decrease in the last-level cache (LLC) capacity may have a detrimental impact on both performance and energy consumption. In this work, we propose a novel technique to enable reliable low voltage operation and preserve capacity for LLCs. In this technique, synergistic cache compression and error correction (Cocoa), we apply compression to LLCs to harvest additional capacity to store ECC check bits. In addition, we introduce a new ECC scheme to minimize the space overhead of ECC. In particular, we employ variable strength ECC on a per-segment basis. In the common case, segments with zero or one bit failures are protected by weak ECC. Few segments with multi-bit failures are protected by strong ECC. Our evaluation for a 2MB 8-way set associative L3 cache shows that the proposed schemes can guarantee reliable cache operation beyond 400mV. Compared to a conventional cache with a Vccmin of 810mV, our schemes reduce the system energy per instruction (Core+L3+DRAM) by 54.5%. Furthermore, we achieve 0.8% higher performance even than a fault-free cache when operating at 400mV. We also demonstrate that our energy benefits remain robust across a broad range of cache sizes and supply voltages.

AB - Voltage scaling is one of the most effective techniques to provide power savings on a chip-wide basis. However, reducing supply voltage in the presence of process variation introduces significant reliability challenges for large SRAM arrays. The rapid decrease in SRAM reliability at low voltages determines a minimum operating voltage (Vccmin). This places a floor on the power consumption of the entire processor. Therefore, processors must either stay at high voltages where the low defect densities are tolerable or work at low voltages with existing fault tolerance schemes which sacrifice a large fraction of the cache capacity for improved reliability. In the latter case, processors could obtain significant energy reduction from the aggressive voltage scaling. However, the decrease in the last-level cache (LLC) capacity may have a detrimental impact on both performance and energy consumption. In this work, we propose a novel technique to enable reliable low voltage operation and preserve capacity for LLCs. In this technique, synergistic cache compression and error correction (Cocoa), we apply compression to LLCs to harvest additional capacity to store ECC check bits. In addition, we introduce a new ECC scheme to minimize the space overhead of ECC. In particular, we employ variable strength ECC on a per-segment basis. In the common case, segments with zero or one bit failures are protected by weak ECC. Few segments with multi-bit failures are protected by strong ECC. Our evaluation for a 2MB 8-way set associative L3 cache shows that the proposed schemes can guarantee reliable cache operation beyond 400mV. Compared to a conventional cache with a Vccmin of 810mV, our schemes reduce the system energy per instruction (Core+L3+DRAM) by 54.5%. Furthermore, we achieve 0.8% higher performance even than a fault-free cache when operating at 400mV. We also demonstrate that our energy benefits remain robust across a broad range of cache sizes and supply voltages.

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KW - Error correcting code

KW - Fault tolerance caches

KW - Voltage scaling

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M3 - Conference contribution

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Yan C, Joseph RE. Cocoa: Synergistic cache compression and error correction in capacity sensitive last level caches. In MEMSYS 2018 - Proceedings of the International Symposium on Memory Systems. Association for Computing Machinery. 2018 https://doi.org/10.1145/3240302.3240304