@inproceedings{a1b8f4e6b5f64a7dab559cd412b56bc1,
title = "Compiler-guided instruction-level clock scheduling for timing speculative processors",
abstract = "Despite the significant promise that circuit-level timing speculation has for enabling operation in marginal conditions, overheads associated with recovery prove to be a serious drawback. We show that fine-grained clock adjustment guided by the compiler can be used to stretch and shrink the clock to maximize benefits of timing speculation and reduce the overheads associated with recovery. We present a formulation for compiler-driven clock scheduling and explore the benefits in several scenarios. Our results show that there are significant opportunities to exploit timing slack when there are appropriate channels for the compiler to select clock period at cycle-level.",
author = "Yuanbo Fan and Tianyu Jia and Jie Gu and Simone Campanoni and Joseph, {Russell E}",
note = "Funding Information: This work was supported by the National Science Foundation under grants CCF-1116610 and CCF-1618065. Publisher Copyright: {\textcopyright} 2018 Association for Computing Machinery.; 55th Annual Design Automation Conference, DAC 2018 ; Conference date: 24-06-2018 Through 29-06-2018",
year = "2018",
month = jun,
day = "24",
doi = "10.1145/3195970.3196013",
language = "English (US)",
isbn = "9781450357005",
series = "Proceedings - Design Automation Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "Proceedings of the 55th Annual Design Automation Conference, DAC 2018",
address = "United States",
}