Abstract
Despite the significant promise that circuit-level timing speculation has for enabling operation in marginal conditions, overheads associated with recovery prove to be a serious drawback. We show that fine-grained clock adjustment guided by the compiler can be used to stretch and shrink the clock to maximize benefits of timing speculation and reduce the overheads associated with recovery. We present a formulation for compiler-driven clock scheduling and explore the benefits in several scenarios. Our results show that there are significant opportunities to exploit timing slack when there are appropriate channels for the compiler to select clock period at cycle-level.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings of the 55th Annual Design Automation Conference, DAC 2018 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Print) | 9781450357005 |
| DOIs | |
| State | Published - Jun 24 2018 |
| Event | 55th Annual Design Automation Conference, DAC 2018 - San Francisco, United States Duration: Jun 24 2018 → Jun 29 2018 |
Publication series
| Name | Proceedings - Design Automation Conference |
|---|---|
| Volume | Part F137710 |
| ISSN (Print) | 0738-100X |
Other
| Other | 55th Annual Design Automation Conference, DAC 2018 |
|---|---|
| Country | United States |
| City | San Francisco |
| Period | 6/24/18 → 6/29/18 |
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ASJC Scopus subject areas
- Computer Science Applications
- Control and Systems Engineering
- Electrical and Electronic Engineering
- Modeling and Simulation
Cite this
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Compiler-guided instruction-level clock scheduling for timing speculative processors. / Fan, Yuanbo; Jia, Tianyu; Gu, Jie; Campanoni, Simone; Joseph, Russell E.
Proceedings of the 55th Annual Design Automation Conference, DAC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. a40 (Proceedings - Design Automation Conference; Vol. Part F137710).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Compiler-guided instruction-level clock scheduling for timing speculative processors
AU - Fan, Yuanbo
AU - Jia, Tianyu
AU - Gu, Jie
AU - Campanoni, Simone
AU - Joseph, Russell E
PY - 2018/6/24
Y1 - 2018/6/24
N2 - Despite the significant promise that circuit-level timing speculation has for enabling operation in marginal conditions, overheads associated with recovery prove to be a serious drawback. We show that fine-grained clock adjustment guided by the compiler can be used to stretch and shrink the clock to maximize benefits of timing speculation and reduce the overheads associated with recovery. We present a formulation for compiler-driven clock scheduling and explore the benefits in several scenarios. Our results show that there are significant opportunities to exploit timing slack when there are appropriate channels for the compiler to select clock period at cycle-level.
AB - Despite the significant promise that circuit-level timing speculation has for enabling operation in marginal conditions, overheads associated with recovery prove to be a serious drawback. We show that fine-grained clock adjustment guided by the compiler can be used to stretch and shrink the clock to maximize benefits of timing speculation and reduce the overheads associated with recovery. We present a formulation for compiler-driven clock scheduling and explore the benefits in several scenarios. Our results show that there are significant opportunities to exploit timing slack when there are appropriate channels for the compiler to select clock period at cycle-level.
UR - http://www.scopus.com/inward/record.url?scp=85053705980&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85053705980&partnerID=8YFLogxK
U2 - 10.1145/3195970.3196013
DO - 10.1145/3195970.3196013
M3 - Conference contribution
SN - 9781450357005
T3 - Proceedings - Design Automation Conference
BT - Proceedings of the 55th Annual Design Automation Conference, DAC 2018
PB - Institute of Electrical and Electronics Engineers Inc.
ER -