Despite the significant promise that circuit-level timing speculation has for enabling operation in marginal conditions, overheads associated with recovery prove to be a serious drawback. We show that fine-grained clock adjustment guided by the compiler can be used to stretch and shrink the clock to maximize benefits of timing speculation and reduce the overheads associated with recovery. We present a formulation for compiler-driven clock scheduling and explore the benefits in several scenarios. Our results show that there are significant opportunities to exploit timing slack when there are appropriate channels for the compiler to select clock period at cycle-level.
|Title of host publication
|Proceedings of the 55th Annual Design Automation Conference, DAC 2018
|Institute of Electrical and Electronics Engineers Inc.
|Published - Jun 24 2018
|55th Annual Design Automation Conference, DAC 2018 - San Francisco, United States
Duration: Jun 24 2018 → Jun 29 2018
|Proceedings - Design Automation Conference
|55th Annual Design Automation Conference, DAC 2018
|6/24/18 → 6/29/18
ASJC Scopus subject areas
- Computer Science Applications
- Control and Systems Engineering
- Electrical and Electronic Engineering
- Modeling and Simulation