Compiler-guided instruction-level clock scheduling for timing speculative processors

Yuanbo Fan, Tianyu Jia, Jie Gu, Simone Campanoni, Russell E Joseph

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Despite the significant promise that circuit-level timing speculation has for enabling operation in marginal conditions, overheads associated with recovery prove to be a serious drawback. We show that fine-grained clock adjustment guided by the compiler can be used to stretch and shrink the clock to maximize benefits of timing speculation and reduce the overheads associated with recovery. We present a formulation for compiler-driven clock scheduling and explore the benefits in several scenarios. Our results show that there are significant opportunities to exploit timing slack when there are appropriate channels for the compiler to select clock period at cycle-level.

Original languageEnglish (US)
Title of host publicationProceedings of the 55th Annual Design Automation Conference, DAC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781450357005
DOIs
StatePublished - Jun 24 2018
Event55th Annual Design Automation Conference, DAC 2018 - San Francisco, United States
Duration: Jun 24 2018Jun 29 2018

Publication series

NameProceedings - Design Automation Conference
VolumePart F137710
ISSN (Print)0738-100X

Other

Other55th Annual Design Automation Conference, DAC 2018
CountryUnited States
CitySan Francisco
Period6/24/186/29/18

Fingerprint

Compiler
Clocks
Timing
Speculation
Scheduling
Recovery
Stretch
Adjustment
Maximise
Cycle
Scenarios
Formulation
Networks (circuits)

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

Cite this

Fan, Y., Jia, T., Gu, J., Campanoni, S., & Joseph, R. E. (2018). Compiler-guided instruction-level clock scheduling for timing speculative processors. In Proceedings of the 55th Annual Design Automation Conference, DAC 2018 [a40] (Proceedings - Design Automation Conference; Vol. Part F137710). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/3195970.3196013
Fan, Yuanbo ; Jia, Tianyu ; Gu, Jie ; Campanoni, Simone ; Joseph, Russell E. / Compiler-guided instruction-level clock scheduling for timing speculative processors. Proceedings of the 55th Annual Design Automation Conference, DAC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. (Proceedings - Design Automation Conference).
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Fan, Y, Jia, T, Gu, J, Campanoni, S & Joseph, RE 2018, Compiler-guided instruction-level clock scheduling for timing speculative processors. in Proceedings of the 55th Annual Design Automation Conference, DAC 2018., a40, Proceedings - Design Automation Conference, vol. Part F137710, Institute of Electrical and Electronics Engineers Inc., 55th Annual Design Automation Conference, DAC 2018, San Francisco, United States, 6/24/18. https://doi.org/10.1145/3195970.3196013

Compiler-guided instruction-level clock scheduling for timing speculative processors. / Fan, Yuanbo; Jia, Tianyu; Gu, Jie; Campanoni, Simone; Joseph, Russell E.

Proceedings of the 55th Annual Design Automation Conference, DAC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. a40 (Proceedings - Design Automation Conference; Vol. Part F137710).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - Despite the significant promise that circuit-level timing speculation has for enabling operation in marginal conditions, overheads associated with recovery prove to be a serious drawback. We show that fine-grained clock adjustment guided by the compiler can be used to stretch and shrink the clock to maximize benefits of timing speculation and reduce the overheads associated with recovery. We present a formulation for compiler-driven clock scheduling and explore the benefits in several scenarios. Our results show that there are significant opportunities to exploit timing slack when there are appropriate channels for the compiler to select clock period at cycle-level.

AB - Despite the significant promise that circuit-level timing speculation has for enabling operation in marginal conditions, overheads associated with recovery prove to be a serious drawback. We show that fine-grained clock adjustment guided by the compiler can be used to stretch and shrink the clock to maximize benefits of timing speculation and reduce the overheads associated with recovery. We present a formulation for compiler-driven clock scheduling and explore the benefits in several scenarios. Our results show that there are significant opportunities to exploit timing slack when there are appropriate channels for the compiler to select clock period at cycle-level.

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Fan Y, Jia T, Gu J, Campanoni S, Joseph RE. Compiler-guided instruction-level clock scheduling for timing speculative processors. In Proceedings of the 55th Annual Design Automation Conference, DAC 2018. Institute of Electrical and Electronics Engineers Inc. 2018. a40. (Proceedings - Design Automation Conference). https://doi.org/10.1145/3195970.3196013