We introduce a new cache architecture that can be used to increase performance and reduce energy consumption in Network Processors. This new architecture is based on the observation that there is a strong correlation between different memory accesses. In other words, if load X and load Y are two consecutively executed load instructions, the offset between the source addresses of these instructions remain usually constant between different iterations. We utilize this information by building a correlating cache architecture. This architecture consists of a Dynamic Correlation Extractor, a Correlation History Table, and a Correlation Buffer. We first show simulation results investigating the frequency of correlating loads. Then, we evaluate our architecture using SimpleScalar/ARM. For a set of representative applications, the correlating cache architecture is able to reduce the average data access time by as much as 52.7% and 36.1% on average, while reducing the energy consumption of the caches by as much as 49.2% and 25.7% on average.
|Original language||English (US)|
|Number of pages||4|
|Journal||Proceedings of the International Symposium on Low Power Electronics and Design|
|State||Published - 2004|
|Event||2004 International Symposium on Low Power Electronics and Design, ISLPED 2004 - Newport Beach, United States|
Duration: Aug 9 2004 → Aug 11 2004
ASJC Scopus subject areas