Design and Implementation of Correlating Caches

Arindam Mallik, Matthew C. Wildrick, Gokhan Memik

Research output: Contribution to journalConference articlepeer-review


We introduce a new cache architecture that can be used to increase performance and reduce energy consumption in Network Processors. This new architecture is based on the observation that there is a strong correlation between different memory accesses. In other words, if load X and load Y are two consecutively executed load instructions, the offset between the source addresses of these instructions remain usually constant between different iterations. We utilize this information by building a correlating cache architecture. This architecture consists of a Dynamic Correlation Extractor, a Correlation History Table, and a Correlation Buffer. We first show simulation results investigating the frequency of correlating loads. Then, we evaluate our architecture using SimpleScalar/ARM. For a set of representative applications, the correlating cache architecture is able to reduce the average data access time by as much as 52.7% and 36.1% on average, while reducing the energy consumption of the caches by as much as 49.2% and 25.7% on average.

Original languageEnglish (US)
Article number1349308
Pages (from-to)58-61
Number of pages4
JournalProceedings of the International Symposium on Low Power Electronics and Design
Issue numberJanuary
StatePublished - 2004
Event2004 International Symposium on Low Power Electronics and Design, ISLPED 2004 - Newport Beach, United States
Duration: Aug 9 2004Aug 11 2004


  • Design
  • Performance

ASJC Scopus subject areas

  • Engineering(all)

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