Design and implementation of correlating caches

Arindam Mallik*, Matthew C. Wildrick, Gokhan Memik

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

We introduce a new cache architecture that can be used to increase performance and reduce energy consumption in Network Processors. This new architecture is based on the observation that there is a strong correlation between different memory accesses. In other words, if load X and load Y are two consecutively executed load instructions, the offset between the source addresses of these instructions remain usually constant between different iterations. We utilize this information by building a correlating cache architecture. This architecture consists of a Dynamic Correlation Extractor, a Correlation History Table, and a Correlation Buffer. We first show simulation results investigating the frequency of correlating loads. Then, we evaluate our architecture using SimpleScalar/ARM. For a set of representative applications, the correlating cache architecture is able to reduce the average data access time by as much as 52.7% and 36.1% on average, while reducing the energy consumption of the caches by as much as 49.2% and 25.7% on average.

Original languageEnglish (US)
Title of host publicationProceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04
Pages58-61
Number of pages4
StatePublished - Dec 1 2004
EventProceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04 - Newport Beach, CA, United States
Duration: Aug 9 2004Aug 11 2004

Other

OtherProceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04
CountryUnited States
CityNewport Beach, CA
Period8/9/048/11/04

Keywords

  • Performance, Design

ASJC Scopus subject areas

  • Engineering(all)

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