Abstract
This paper presents performance results for the design and implementation of parallel pipelined Space-Time Adaptive Processing (STAP) algorithms on parallel computers. In particular, the paper describes the issues involved in parallelization, our approach to parallelization and performance results on an Intel Paragon. The paper also discusses the process of developing software for such an application on parallel computers when latency and throughput are both considered together and presents tradeoffs considered with respect to inter and intra-task communication and data redistribution. The results show that not only scalable performance was achieved for individual component tasks of STAP but linear speedups were obtained for the integrated task performance, both for latency as well as throughput. Results are presented for up to 236 compute nodes (limited by the machine size available to us). Another interesting observation made from the implementation results is that performance improvement due to the assignment of additional processors to one task can improve the performance of other tasks without any increase in the number of processors assigned to them. Normally, this cannot be predicted by theoretical analysis.
Original language | English (US) |
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Title of host publication | Proceedings of the International Parallel Processing Symposium, IPPS |
Publisher | IEEE Comp Soc |
Pages | 220-225 |
Number of pages | 6 |
ISBN (Print) | 0818684046 |
DOIs | |
State | Published - 1998 |
Event | Proceedings of the 1998 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing - Orlando, FL, USA Duration: Mar 30 1998 → Apr 3 1998 |
Other
Other | Proceedings of the 1998 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing |
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City | Orlando, FL, USA |
Period | 3/30/98 → 4/3/98 |
ASJC Scopus subject areas
- Hardware and Architecture