Design Planning in Hardware Compilers

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Along with the fast evolution of programmable and reconfigurable systems, hardware compilers also advanced towards enhanced capabilities and optimization power. The responsibility of early hardware compilers was to map a subset of procedures or time critical computations onto hardware, where reconfigurable hardware was mostly utilized as a co-processing unit. A new generation of hardware compilers are needed to create frameworks for mapping significantly complex applications onto programmable devices. This can be achieved by empowering hardware compilers with new methodologies to increase their efficiency. Design Planning is one such concept. In this paper, we introduce techniques to enable a smooth, non-restrictive interaction between different compilation stages. These techniques are collectively referred to as Design Planning.

Original languageEnglish (US)
Title of host publicationProceedings of the Fifteenth IASTED International Conference on Parallel and Distributed Computing and Systems
EditorsT. Gonzalez
Pages910-915
Number of pages6
Edition2
StatePublished - Dec 1 2003
EventProceedings of the Fifteenth IASTED International Conference on Parallel and Distributed Computing and Systems - Marina del Rey, CA, United States
Duration: Nov 3 2003Nov 5 2003

Publication series

NameProceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems
Number2
Volume15

Other

OtherProceedings of the Fifteenth IASTED International Conference on Parallel and Distributed Computing and Systems
CountryUnited States
CityMarina del Rey, CA
Period11/3/0311/5/03

Keywords

  • Hardware Compiler
  • High-level Synthesis
  • Reconfigurable Systems

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications

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