TY - GEN
T1 - Double DIP
T2 - 27th Great Lakes Symposium on VLSI, GLSVLSI 2017
AU - Shen, Yuanqi
AU - Zhou, Hai
N1 - Publisher Copyright:
© 2017 ACM.
PY - 2017/5/10
Y1 - 2017/5/10
N2 - Logic encryption is a hardware security technique that uses extra key inputs to lock a given combinational circuit. A recent study by Subramanyan et al. shows that all existing logic encryption techniques can be successfully attacked. As a countermeasure, SARLock was proposed to enhance the security of existing logic encryptions. In this paper, we reevaluate the security of these approaches. A SAT-based attack called Double DIP is proposed and shown to successfully defeat SARLock-enhanced encryptions.
AB - Logic encryption is a hardware security technique that uses extra key inputs to lock a given combinational circuit. A recent study by Subramanyan et al. shows that all existing logic encryption techniques can be successfully attacked. As a countermeasure, SARLock was proposed to enhance the security of existing logic encryptions. In this paper, we reevaluate the security of these approaches. A SAT-based attack called Double DIP is proposed and shown to successfully defeat SARLock-enhanced encryptions.
UR - http://www.scopus.com/inward/record.url?scp=85021228051&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85021228051&partnerID=8YFLogxK
U2 - 10.1145/3060403.3060469
DO - 10.1145/3060403.3060469
M3 - Conference contribution
AN - SCOPUS:85021228051
T3 - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
SP - 179
EP - 184
BT - GLSVLSI 2017 - Proceedings of the Great Lakes Symposium on VLSI 2017
PB - Association for Computing Machinery
Y2 - 10 May 2017 through 12 May 2017
ER -