Dynamic directories: A mechanism for reducing on-chip interconnect power in multicores

Abhishek Das*, Matt Schuchhardt, Nikos Hardavellas, Gokhan Memik, Alok Nidhi Choudhary

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

On-chip interconnection networks consume a significant fraction of the chip's power, and the rapidly increasing core counts in future technologies is going to further aggravate their impact on the chip's overall power consumption. A large fraction of the traffic originates not from data messages exchanged between sharing cores, but from the communication between the cores and intermediate hardware structures (i.e., directories) for the purpose of maintaining coherence in the presence of conflicting updates. In this paper, we propose Dynamic Directories, a method allowing the directories to be placed arbitrarily in the chip by piggy-backing the virtual to physical address translation. This eliminates a large fraction of the on-chip interconnect traversals, hence reducing the power consumption. Through trace-driven and cycle-accurate simulation in a range of scientific and Map-Reduce applications, we show that our technique reduces the power and energy expended by the on-chip interconnect by up to 37% (16.4% on average) with negligible hardware overhead and a small improvement in performance (1.3% on average).

Original languageEnglish (US)
Title of host publicationProceedings - Design, Automation and Test in Europe Conference and Exhibition, DATE 2012
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages479-484
Number of pages6
ISBN (Print)9783981080186
DOIs
StatePublished - 2012
Event15th Design, Automation and Test in Europe Conference and Exhibition, DATE 2012 - Dresden, Germany
Duration: Mar 12 2012Mar 16 2012

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Other

Other15th Design, Automation and Test in Europe Conference and Exhibition, DATE 2012
Country/TerritoryGermany
CityDresden
Period3/12/123/16/12

Keywords

  • Multicore architecture
  • Non-uniform caches
  • On-chip networks

ASJC Scopus subject areas

  • Engineering(all)

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