Dynamic template generation for resource sharing in control and data flow graphs

David C. Zaretsky*, Gaurav Mittal, Robert P. Dick, Prith Banerjee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

High-level synthesis compilers often produce reoccurring patterns in intermediate CDFGs during translation. By identifying large reoccurring patterns, one may reduce area and communication overhead by efficiently reusing hardware for multiple operations. This paper presents an algorithm for dynamically generating templates of reoccurring patterns for resource sharing in CDFGs. Results show 40-80% resource reduction using small, incremental template growth, and variations within a 5% margin among varying look-ahead depths.

Original languageEnglish (US)
Title of host publicationProceedings - 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Pages465-468
Number of pages4
DOIs
StatePublished - 2006
Event19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design - Hyderabad, India
Duration: Jan 3 2006Jan 7 2006

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
Volume2006
ISSN (Print)1063-9667

Conference

Conference19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Country/TerritoryIndia
CityHyderabad
Period1/3/061/7/06

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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