TY - GEN
T1 - Dynamic template generation for resource sharing in control and data flow graphs
AU - Zaretsky, David C.
AU - Mittal, Gaurav
AU - Dick, Robert P.
AU - Banerjee, Prith
PY - 2006
Y1 - 2006
N2 - High-level synthesis compilers often produce reoccurring patterns in intermediate CDFGs during translation. By identifying large reoccurring patterns, one may reduce area and communication overhead by efficiently reusing hardware for multiple operations. This paper presents an algorithm for dynamically generating templates of reoccurring patterns for resource sharing in CDFGs. Results show 40-80% resource reduction using small, incremental template growth, and variations within a 5% margin among varying look-ahead depths.
AB - High-level synthesis compilers often produce reoccurring patterns in intermediate CDFGs during translation. By identifying large reoccurring patterns, one may reduce area and communication overhead by efficiently reusing hardware for multiple operations. This paper presents an algorithm for dynamically generating templates of reoccurring patterns for resource sharing in CDFGs. Results show 40-80% resource reduction using small, incremental template growth, and variations within a 5% margin among varying look-ahead depths.
UR - http://www.scopus.com/inward/record.url?scp=33748572970&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33748572970&partnerID=8YFLogxK
U2 - 10.1109/VLSID.2006.75
DO - 10.1109/VLSID.2006.75
M3 - Conference contribution
AN - SCOPUS:33748572970
SN - 0769525024
SN - 9780769525020
T3 - Proceedings of the IEEE International Conference on VLSI Design
SP - 465
EP - 468
BT - Proceedings - 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
T2 - 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Y2 - 3 January 2006 through 7 January 2006
ER -