Efficient synthesis of array intensive computations onto FPGA based accelerators

N. Shenoy*, P. Banerjee, A. Choudhary, M. Kandemir

*Corresponding author for this work

Research output: Contribution to conferencePaper

Abstract

Array intensive computations are characterized by processing of large arrays stored in external memory in multiple loops. Synthesizing these computations onto FPGAs involves automatic translation of the behavioral description into state machines controlled by a clock such that the execution time of the program as a whole is the minimum and area requirement does not exceed a predefined limit. The synthesis algorithm also needs to efficiently sequence the array accesses taking into account memory access requirements such as pipelining. In this paper we present two algorithms each with a specific emphasis to handle this synthesis problem. Our heuristic algorithm generates good solutions in a very short time (less than a second), while our Mixed Integer Linear Programming (MILP) based algorithm can generate optimal solution given sufficient time. Both to, to minimize execution time and area. Our algorithms not only look at individual loops to exploit parallelism but also consider them together while deciding the clock. The overall execution time is minimized and not just the number of cycles or the cycle time. They also efficiently synthesize memory accesses to fully, exploit the memory pipelining. We compare these two algorithms in terms of their relative strengths.

Original languageEnglish (US)
Pages305-310
Number of pages6
StatePublished - Jan 1 2001
Event14th International Conference on VLSI Design (VLSI DESIGN 2001) - Bangalore, India
Duration: Jan 3 2001Jan 7 2001

Other

Other14th International Conference on VLSI Design (VLSI DESIGN 2001)
CountryIndia
CityBangalore
Period1/3/011/7/01

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Shenoy, N., Banerjee, P., Choudhary, A., & Kandemir, M. (2001). Efficient synthesis of array intensive computations onto FPGA based accelerators. 305-310. Paper presented at 14th International Conference on VLSI Design (VLSI DESIGN 2001), Bangalore, India.