Electrical property comparison and charge transmission in p-type double gate and single gate junctionless accumulation transistor fabricated by AFM nanolithography

Arash Dehzangi*, Ahmad Makarimi Abdullah, Farhad Larki, Sabar D. Hutagalung, Elias B. Saion, Mohd N. Hamidon, Jumiah Hassan, Yadollah Gharayebi

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

24 Scopus citations

Abstract

The junctionless nanowire transistor is a promising alternative for a new generation of nanotransistors. In this letter the atomic force microscopy nanolithography with two wet etching processes was implemented to fabricate simple structures as double gate and single gate junctionless silicon nanowire transistor on low doped p-type silicon-on-insulator wafer. The etching process was developed and optimized in the present work compared to our previous works. The output, transfer characteristics and drain conductance of both structures were compared. The trend for both devices found to be the same but differences in subthreshold swing, 'on/off' ratio, and threshold voltage were observed. The devices are 'on' state when performing as the pinch off devices. The positive gate voltage shows pinch off effect, while the negative gate voltage was unable to make a significant effect on drain current. The charge transmission in devices is also investigated in simple model according to a junctionless transistor principal.

Original languageEnglish (US)
Article number381
Pages (from-to)2-23
Number of pages22
JournalNanoscale Research Letters
Volume7
DOIs
StatePublished - 2012

Keywords

  • Atomic force microscopy
  • Double gate
  • Junctionless transistors
  • Local anodic oxidation
  • Silicon-oninsulator
  • Single gate junctionless silicon nanowire transistor

ASJC Scopus subject areas

  • Materials Science(all)
  • Condensed Matter Physics

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