Advanced semiconductors continue to increase performance by increasing functional integration and clock speed. Not only is the total power consumption increasing, the power distribution is highly non-uniform over the die area. Continued reduction in design rules are likely to increase the non-uniformity of the power density as high-speed circuits that dissipate a large amount of power but consume a small amount of die area are surrounded by lower-speed circuits that dissipate little power but consume a larger die area. The high temperature of localized hot spots adversely affects product reliability, performance and yield. A promising approach for site-specific cooling of hot spots is use of an embedded thermoelectric cooler (eTEC). The thickness of super lattice thermoelectric material is typically less than 20μm, which provides very high heat flux (>300 W/cm 2). The eTEC can be unobtrusively integrated in the package between the die and heat spreader. On-demand, site-specific cooling and the high coefficient-of-performance (COP) of the eTEC minimize the active power required for cooling hot spots.