Emitter-coupled spin-transistor logic

Joseph S. Friedman*, Yehea I. Ismail, Gokhan Memik, Alan Varteres Sahakian, Bruce W Wessels

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

The recent invention of magnetoresistive bipolar spin-transistors makes possible the creation of new spintronic logic families. Here we propose the first logic family exploiting these spin-transistors, extending emitter-coupled logic (ECL) to achieve a greater range of basis logic functions. By placing the wire from the output stage of ECL logic elements near spin-transistors in other parts of a circuit, additional basis logic elements can be realized. These new logic elements support greater logic minimization, resulting in enhanced speed, area, and power characteristics. A novel magnetic shielding structure provides this logic family with the crucial ability to cascade logic stages. This logic family achieves a power-delay product 10 to 25 times smaller than conventional ECL, and can therefore be exploited to increase the performance of very high-speed circuits while broadening the range of design choices for a variety of electronic applications.

Original languageEnglish (US)
Title of host publicationProceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012
Pages139-145
Number of pages7
StatePublished - Dec 1 2012
Event2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012 - Amsterdam, Netherlands
Duration: Jul 4 2012Jul 6 2012

Publication series

NameProceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012

Other

Other2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012
CountryNetherlands
CityAmsterdam
Period7/4/127/6/12

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ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Friedman, J. S., Ismail, Y. I., Memik, G., Sahakian, A. V., & Wessels, B. W. (2012). Emitter-coupled spin-transistor logic. In Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012 (pp. 139-145). [6464155] (Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2012).