Engineering over-clocking: Reliability-performance trade-offs for high-performance register files

Gokhan Memik, Masud H. Chowdhury, Arindam Mallik, Yehea I. Ismail

Research output: Contribution to conferencePaperpeer-review

21 Scopus citations


Register files are in the critical path of most high-performance processors and their latency is one of the most important factors that limit their size. Our goal is to develop error correction mechanisms at the architecture level. Utilizing this increased robustness, the clock frequencies of the circuits are pushed beyond the point of allowing full voltage swing. This increases the errors observed due to noise and other external factors. The resulting errors are then corrected through the error correction mechanisms. We first develop a realistic model for error probability in register files for a given clock frequency. Then, we present the overall architecture, which allows the error detection computation to be overlapped with other computation in the pipeline. We develop novel techniques that utilize the fact that at a given instance many physical registers are not used in superscalar processors. These underutilized registers are used to store the values of active registers. Our simulation results show that for a fixed architecture the access times to the registers can be reduced by as much as 80% while increasing the number of execution cycles by 0.12%. On the other hand, by reducing the register file access pipeline stages by 75%, the average number of execution cycles of SPEC applications can be reduced by 11.5%.

Original languageEnglish (US)
Number of pages10
StatePublished - 2005
Event2005 International Conference on Dependable Systems and Networks - Yokohama, Japan
Duration: Jun 28 2005Jul 1 2005


Other2005 International Conference on Dependable Systems and Networks


  • Adaptive Systems
  • Fault-Tolerant Computing
  • Reliability

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications


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